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DP83266 Datasheet(PDF) 130 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 130 Page - National Semiconductor (TI) |
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130 / 152 page  70 Control Information (Continued) Pool Space Descriptor (PSP) Pool Space Descriptors (PSPs) contain the address of a free space in host memory available for writing Input Data Units The count field is not used The space is assumed to end at the next 4 kByte boundary When PSPs are read by the MACSI device the address field of the PSP is loaded into the Indicate Channel’s IDU Pointer Register and is used as the address for the IDU memory write 31 30 29 28 27 13 12 0 RES CNT Word 0 F-L RES LOC Word 1 Bit Symbol Description Word 0 D12 – D0 CNT Byte Count Number of bytes of available memory area (this field is currently not used by the MACSI device) To ensure software compatibility with future devices which may use this field this field may be written with the number of bytes from PSPLOC to the next 4 kByte boundary D31 – D13 RES Reserved Word 1 D27 – D0 LOC Location Memory byte address of memory area available for writing IDUs Normally the page offset will be Zero to simplify space management Must be burst aligned to the size of the largest burst enabled (4 word or 8 word) D29 – D28 RES Reserved D31 – D30 F-L FirstLast Tag Identifies the PSP part should be PSPOnly (ie F-L e 11) 130 |
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