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DP83266 Datasheet(PDF) 132 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 132 Page - National Semiconductor (TI) |
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132 / 152 page ![]() 80 Signal Descriptions (Continued) 82 PHY INTERFACE The PHY Interface signals transfer symbol pairs between the MACSI and PLAYERa devices Transfers are synchronous using the 125 MHz Local Byte Clock signal (signal provided by the PLAYERa device) A control bit is used to indicate if a Data symbol pair or Control symbol pair or a mixed ControlData symbol pair are being transferred Parity is generated on the PH Indicate and MA Indicate data Parity is checked on the PH Request and MA Request data Symbol Pin IO Description PRP 122 O PHY Request Parity Odd parity for PRC and PRD7 – 0 PRC 120 O PHY Request Control 0 Indicates PRD7 – 0 contains a Data symbol pair 1 Indicates PRD7 – 0 contains a Control or mixed ControlData symbol pair PRD7 – PRD0 118 116 114 O PHY Request Data Contains a Data or Control symbol pair 110 108 106 104 102 PIP 123 I PHY Indicate Parity Odd parity for PIC and PID7 – 0 PIC 121 I PHY Indicate Control 0 Indicates PRD7 – PRD0 contains a Data symbol pair 1 Indicates PRD7 – PRD0 contains a Control or mixed ControlData symbol pair PID7 – PID0 119 117 115 I PHY Indicate Data Contains a Data or a mixed ControlData symbol pair 111 109 107 105 103 132 |
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