DP83266 datasheet(135/152 Pages) NSC

135 / 152 page

80 Signal Descriptions (Continued)

83 EXTERNAL MATCHING INTERFACE

The External Matching Interface provides the means to add external address recognition logic The results of these address

comparisons are conveyed on the appropriate signals

Symbol

Description

ECIP

External Compare In Progress

This signal is asserted to indicate that external address

comparison has begun It is deasserted to indicate that the comparison has completed ECOPY

and EM are sampled on the rising edge of LBC1 after the deassertion of ECIP ECIP must be

asserted before the seventh byte of the INFO field in order for the MACSI device to recognize an

external comparison It must be deasserted for at least one cycle for the external comparison to

complete If ECIP has not been deasserted before two bytes after the End Delimiter (ED from the

PLAYERa device) the MACSI device will not copy this frame ECIP may be implemented as a

positive or negative pulse Note that ECIP will affect the operation of the MACSI device even if the

external copy mode is not specifically selected See Section 63 on page 30 for more details on the

external matching interface

ECOPY

External Copy

Indicates that the current frame should be copied if possible Sampled on the

rising edge of LBC1 after ECIP is deasserted

External Destination Address Match

Indicates that an explicit match occurred on the current

frame This affects the setting of the A indicator for this frame Sampled one byte time before ED is

received by the Ring Engine

External Source Address Match

Indicates that the current frame was transmitted by this station

and should be stripped The Ring Engine will begin stripping three byte times after the assertion of

EM The Service Engine samples EM on the rising edge of LBC1 after the deassertion of ECIP

LEARN

Learn

Provided for transparent bridging applications Indicates that the current frame should be

copied and the Source Address be added to the address filter database if not already present This

signal is asserted for Long Address frames which were not sourced by this station If frames are

sent using Source Address Transparency (SAT) using the My

Void stripping mechanism Learn

will be false from the transmission of the first SAT frame until after the My

Void frame is received

Learn is valid at the ‘‘INFO Received’’ point for each frame This is when the fourth byte of INFO

field passes between the Ring Engine and the System Interface This occurs three byte-times after

the fourth byte of the INFO field passes between the PLAYERa device and the MACSI device

AFINHIB

AFLAG Inhibit

For MACSI Revision D or later this pin allows the User to suppress internal

address recognition on individual frames By asserting this pin before the 7th byte of the INFO field

(as measured at the PID interface) the User can block the AFLAG signal between the MAC and

the System Interface For the MACSI to recognize this pin the User must assert the MAC Mode

Connect pin

84 LED INTERFACE

These signals provide a means for controlling status LEDs to give a visual indication of transmit and receive activity Since the

LED control pins use open-drain output structures the User must supply pull-up resistors This interface is only available on

MACSI Revision D or later

Symbol

Description

TXLED

Transmit LED

The MACSI will assert this pin when it detects that the Request State machine has

entered the ‘‘sending’’ state (once per transmitted frame) Note that the MACSI device will not

assert TXLED for internally generated MAC frames This pin will not drive an LED directly The User

must supply a one-shot circuit to create a pulse long enough to make the LED visible

RXLED

Receive LED

The MACSI will assert this pin when it detects the End Delimiter of a copied frame

(VCOPY and EDRCVD) This pin will not drive an LED directly The User must supply a one-shot

circuit to create a pulse long enough to make the LED visible

135

DP83266 Datasheet(PDF) 135 Page - National Semiconductor (TI)

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