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DP83266 Datasheet(PDF) 137 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 137 Page - National Semiconductor (TI) |
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137 / 152 page  80 Signal Descriptions (Continued) Bus Control Symbol Pin IO Description AB AS 39 O ABus Address Strobe When first asserted this TRI-STATE signals indicates that address on AB AD is valid When this signal is inactive and AB ACK is asserted the next cycle is a Recovery State (Tr) in which the bus arbiter can sample all bus requests then issue a bus grant in the following cycle Note that the timing of this signal is under software control via Mode Register 1 (MR1) AB RW 35 O ABus ReadWrite This TRI-STATE signal determines the current direction of an ABus access A high level indicates a read access and a low level indicates a write access AB DEN 34 IO ABus Data Enable In normal ABus mode this TRI-STATE signal indicates that data on AB AD31 – 0 is valid In the enhanced ABus mode for SBus this signal is an additional Acknowledgment input AB SIZ2 – 0 31-29 O ABus Size These TRI-STATE signals indicate the size of the transfer on AB AD31-0 encoded as follows Transfer AB SIZ2 AB SIZ1 AB SIZ0 Size 0 0 0 4 Bytes 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 16 Bytes 1 0 1 32 Bytes 1 1 0 Reserved 1 1 1 Reserved AB ACK 37 I ABus Acknowledge Indicates a bus slave’s response to a bus master The meaning of this signal depends on the state of ABus Error (AB ERR) as well as the ABus mode selected (normal or enhanced) The exact function is described below AB ERR 36 I ABus Error In normal ABus mode this signal is asserted by a bus slave to cause a transaction retry or transaction abort In the enhanced ABus mode for SBus this signal together with AB ACK and AB DEN encode the acknowledgment type The encoding is as follows EAM e 0 EAM e 1 AB ACK AB ERR AB ACK AB DEN AB ERR Function Ack(2) Ack(1) Ack(0) 1 1 1 1 1 Wait Cycle 0 1 0 1 1 Word Acknowledgement 0 0 1 0 0 Retry 1 0 1 1 0 Error 0 0 0 Not Supported 0 0 1 Not Supported 0 1 0 Not Supported 1 0 1 Not Supported Bus Arbitration Symbol Pin IO Description AB BR 28 O ABus Bus Request This signal is used by the MACSI device to request use of the ABus AB BG 27 I ABus Grant This signal is asserted by external bus arbitration logic to grant use of the ABus to the MACSI device If AB BG is asserted at the start of a transaction (Tbr) the MACSI device will run a transaction Note that in normal ABus mode (MR1EAM e 0) the MACSI device may take up to two cycles to respond to AB BG Therefore AB BG should not be removed until the MACSI device has indicated that it has sampled AB BG and taken the bus (this can be determined with AB AS for example) AB CLK 38 I ABus Clock All ABus operations are synchronized to the rising edge of AB CLK 137 |
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