AD9726 datasheet(5/24 Pages) AD

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AD9726

Rev. A | Page 5 of 24

DIGITAL SIGNAL SPECIFICATIONS

DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference,

TMIN to TMAX, unless otherwise specified.

Table 3.

Parameter

Min

Typ

Max

Unit

DAC CLOCK INPUTS (CLK+/–)

Differential Voltage

0.5

1.0

Common-Mode Voltage

1.0

1.25

LVDS INPUTS (DB[15:0]+/–, DCLK_IN+/–)

Input Voltage Range

825

1575

Differential Threshold Voltage

100

Differential Input Impedance

100

Ω

LVDS OUTPUT (DCLK_OUT+/–)

Differential Output Voltage1

250

400

Offset Voltage

1.0

1.2

Short-Circuit Output Current

CMOS INPUTS (CSB, SCLK, SDIO, RESET)

Logic 0 Voltage

0.5

Logic 1 Voltage

2.5

Input Current

CMOS OUTPUTS (SDO, SDIO)

Logic 0 Voltage

0.5

Logic 1 Voltage

3.0

Short-Circuit Output Current

CONTROL INPUTS (SPI_DIS, SDR_EN)

Logic 0 Voltage

0.5

Logic 1 Voltage

2.0

Input Current

1 With 100 Ω external load.

TIMING SPECIFICATIONS

DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference,

TMIN to TMAX, unless otherwise specified.

Table 4.

Parameter

Min

Typ

Max

Unit

LVDS DATA BUS

DDR DCLK_OUT+/– Propagation Delay (tDCPD-DDR)

2000

DDR DB[15:0]+/– Set-Up Time (tDSU-DDR)

–100

DDR DB[15:0]+/– Hold Time (tDH-DDR)

500

SDR DCLK_OUT+/– Propagation Delay (tDCPD-SDR)

300

SDR DB[15:0]+/– Set-Up Time (tDSU-SDR)

–100

SDR DB[15:0]+/– Hold Time (tDH-SDR)

500

SERIAL PORT INTERFACE

SCLK Frequency (fSCLK)

MHz

SCLK Rise/Fall Time

SCLK Pulse Width High (tCPWH)

SCLK Pulse Width Low (tCPWL)

SCLK Set-Up Time (tCSU)

SDIO Set-Up Time (tDSU)

SDIO Hold Time (tDH)

SDIO/SDO Valid Time (tDV)

RESET PULSE WIDTH

1.5

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