AD9726 datasheet(21/24 Pages) AD

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AD9726

Rev. A | Page 21 of 24

Sync Manual Mode

In fully automatic mode, the AD9726 both detects when a

resynchronization is necessary and initiates an update. In

manual mode, automatic updating is disabled. Enable manual

mode by setting the SYNCMAN bit in SPI Register 0x02.

In manual mode, the sync logic still monitors incoming data

and the DAC clock, but it indicates the need for an update by

asserting the SYNCALRM bit. In this mode, the user is

expected to regularly poll the SYNCALRM bit. When this bit

is read back high, the user can issue a manual sync update also

by asserting the SYNCUPD bit in SPI Register 0x02.

SYNCALRM does not indicate that data is being lost but that

conditions are close to the point where data may be lost. The

sync logic should be resynchronized by asserting SYNCUPD

at the next convenient time.

In manual mode, users can choose when to update the sync

logic. When operating with burst data, issuing a sync update

between active bursts updates the system without risking the

loss of any data. In fact, because SYNCUPD always forces a

resynchronization regardless of operational mode, even users in

fully automatic mode can reduce the possibility of data loss by

occasionally forcing a sync update during idle activity.

If either the data clock or the DAC clock is interrupted for any

reason, a SYNCUPD should always be executed to ensure that

data bus and DAC clock phase alignment remains optimized.

SYNC External Mode

Going beyond manual mode, sync external mode offers a

greater level of control and can be useful if multiple DAC

channels are employed in an application. Enable sync external

mode by asserting the SYNCEXT bit in SPI Register 0x16.

Manual mode must also be enabled.

The four channels into which each incoming data-word is

multiplexed are called quadrants. In any mode, the current

quadrant value can always be read back via SYNCOUT (Bits

[1:0] of SPI Register 0x15). At sync update, the logic chooses the

optimal quadrant and refreshes the value of SYNCOUT.

It is also possible to enter a value into SYNCIN (Bits [4:3] of SPI

ates as expected, except that the quadrant value in SYNCIN is

used following an update. This can be used to align delays

between multiple device outputs.

Operating With SPI Disabled

If the SPI_DIS pin is connected high to ADVDD and the SPI is

disabled, the sync logic is placed into manual mode.

SYNCALRM status can then be monitored in hardware via the

unused SPI pin SDO (54), and SYNCUPD requests can be

entered in hardware via the unused SPI pin SCLK (56). If these

two pins are connected together, fully automatic sync operation

can be achieved.

AD9726 Datasheet(PDF) 21 Page - Analog Devices

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