AD9726 datasheet(8/24 Pages) AD

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AD9726

Rev. A | Page 8 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REXT

CLKVDD

CLKGND

CLK–

CLK+

CLKVDD

DGND

DVDD

DB15+

DB14+

DB14–

DB13+

DB13–

DB12+

DB12–

DB11+

DB11–

DBVDD

DB15–

REFIO

RESET

CSB

SDO (SYNCALRM)

SDIO

SCLK (SYNCUPD)

FSADJ

DGND

DVDD

DB0–

DB1–

DB1+

DB2–

DB2+

DB3–

DB3+

DB4–

DB4+

DBGND

DB0+

PIN 1

21 22 23

24 25 26 27

28 29 30

31 32 33 34 35 36 37 38 39 40

80 79

76 75 74

73 72 71

70 69 68 67 66 65 64 63 62 61

AD9726

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 7. Pin Function Descriptions

No.

Mnemonic

Description

CLKVDD

Clock Supply Voltage

REXT

Sets Data Clock Output Drive1

CLKVDD

Clock Supply Voltage

CLKGND

Clock Supply Common

CLK+

DAC Clock Input True

CLK−

DAC Clock Input Complement

CLKGND

Clock Supply Common

DGND

Digital Supply Common

DVDD

Digital Supply Voltage

DB15+

Data Bit 15 True

DB15−

Data Bit 15 Complement

DB14+

Data Bit 14 True

DB14−

Data Bit 14 Complement

DB13+

Data Bit 13 True

DB13−

Data Bit 13 Complement

DB12+

Data Bit 12 True

DB12−

Data Bit 12 Complement

DB11+

Data Bit 11 True

DB11−

Data Bit 11 Complement

DBVDD

Data Bus Supply Voltage

DBGND

Data Bus Supply Common

No.

Mnemonic

Description

DB10+

Data Bit 10 True

DB10−

Data Bit 10 Complement

DB9+

Data Bit 9 True

DB9−

Data Bit 9 Complement

DB8+

Data Bit 8 True

DB8−

Data Bit 8 Complement

DCLK_OUT+

Data Clock Output True

DCLK_OUT−

Data Clock Output Complement

DBVDD

Data Bus Supply Voltage

DBGND

Data Bus Supply Common

DCLK_IN+

Data Clock Input True

DCLK_IN−

Data Clock Input Complement

DB7+

Data Bit 7 True

DB7−

Data Bit 7 Complement

DB6+

Data Bit 6 True

DB6−

Data Bit 6 Complement

DB5+

Data Bit 5 True

DB5−

Data Bit 5 Complement

DBVDD

Data Bus Supply Voltage

DBGND

Data Bus Supply Common

DB4+

Data Bit 4 True

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