AD9726 datasheet(18/24 Pages) AD

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AD9726

Rev. A | Page 18 of 24

For multibyte transfers with MSB justification, the address in

the instruction byte is interpreted as a final address, and its value

is decremented automatically by the controller. For multibyte

transfers with LSB justification, the address in the instruction

byte is interpreted as an initial address, and its value is incremented

automatically by the controller.

Care must be exercised when switching from MSB to LSB

justification. The controller switches modes immediately once

all eight bits of SPI Register 0x00 are written (even if in the

process of a multibyte transfer). For this reason, a single byte

command is recommended when changing justification.

3-Wire and 4-Wire Operation

Bit 7 of SPI Register 0x00 defaults low, enabling 4-wire SPI

operation. In this mode, serial data is input from the SDIO pin,

and serial data is output on the SDO pin. Setting Bit 7 of SPI

SDIO becomes bidirectional and switches automatically from

input to output when necessary. The SDO pin in this mode is

unused and assumes a high impedance state.

As with MSB or LSB justification, care must be exercised when

switching operational modes. The change occurs immediately

once all eight bits of SPI Register 0x00 are written.

Writing and Reading Register Data

Bringing CSB low initiates a new communication cycle. The

next eight rising edges of SCLK latch data from SDIO into the

instruction byte. If Bit 7 of the instruction byte is low, a write

operation is enabled. If Bit 7 is high, a read operation is enabled.

For a write operation, a data byte is latched from the SDIO pin

into a register on the next eight rising edges of SCLK. If the

instruction byte Bit 6 and Bit 5 are not both 0, a multibyte

transfer latches data bytes into adjacent registers after each

successive set of eight rising SCLK edges. Depending upon

MSB or LSB justification, the controller decrements or

increments the address value in the instruction byte during

the cycle as necessary.

If a read operation is enabled, data bits from the register being

addressed appear on SDO (or SDIO) with each falling edge of

SCLK. Note that for a read operation, the eighth bit of the

instruction byte is latched on the eighth rising edge of SCLK

and the first output bit is enabled on the immediately following

falling SCLK edge.

For multibyte read sequences, the controller adjusts the register

address when necessary and subsequent data bit values appear

at the output with each falling SCLK edge.

Disabling the SPI

Tie the SPI_DIS pin high to ADVDD to disable the serial port

interface. In this state, the default DDR operational mode can be

changed to SDR by pulling the SDR_EN pin high to ADVDD. In

addition, with the SPI disabled, the sync logic no longer operates

in a fully automatic mode. See the Sync Logic Operation and

Programming section for a full explanation of sync operational

modes.

SPI PIN DESCRIPTION

The AD9726 SPI logic runs from the DBVDD supply rail, and

input/output thresholds are based upon a nominal 3.3 V level.

The maximum frequency of operation is 15 MHz.

Chip Select (CSB)

The CSB pin is an active low input. It begins and ends any

communication cycle and must remain low during the entire

cycle. An incomplete cycle is aborted if CSB is prematurely

returned high .

Serial Clock (SCLK)

The SCLK pin is used to synchronize data to and from the SPI

registers and the controller state machine runs from this input.

It is therefore possible to read and write register data (but not

SMEM/FMEM) without a valid DAC clock. All input data is

registered on the rising edge of SCLK and output data bits are

enabled on the falling edge of SCLK.

Serial Data Input/Output (SDIO)

Data is always written into the SPI on the SDIO pin. In 3-wire

mode however, data is also driven out using this pin. The switch

from input to output occurs automatically between the instruct-

ion and data transfer phases of a read operation. In the default

4-wire mode, SDIO is unidirectional and input only.

Serial Data Output (SDO)

Serial data is driven out on the SDO pin when the SPI is in its

default 4-wire mode. In 3-wire mode (or whenever CSB is high)

SDO is set to a high impedance state.

CALIBRATION

To ensure linearity to the 16-bit level, the AD9726 incorporates

132 calibration DACs (CALDACs), which are used to linearize

the current output transfer function. Each CALDAC is a 6-bit

device and takes its input directly from static memory (SMEM).

There are 127 CALDACs associated with each major transition

of the 16-bit input data-word (that is, any transition involving

the upper 7 MSBs). A 128th CALDAC operates on the sum total

of the lower 9 LSBs. The remaining 4 CALDACs (129 to 132)

are used to adjust the DAC’s overall transfer function gain.

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