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AD9726

Rev. A | Page 20 of 24

Self Calibration

The AD9726 features an internal self-calibration engine to

linearize the transfer function automatically. This can be very

useful at temperature extremes where factory calibration no

longer applies. The automated cycle can be initiated by asserting

the SELFCAL bit.

The self-calibration process calibrates all linearity and gain

CALDACs based upon a fixed internal reference current. Values

for all CALDACs are stored in volatile static memory. The

CALSTAT bit indicates the successful completion of the cycle,

and the SELFCAL bit is cleared. Following the cycle, the device

reports a self-calibrated state (CALMEM = 01b).

As with MEMXFER, successful assertion of the SELFCAL bit

requires that Bits [3:0] of Register 0x0F be clear. If any of these

bits are asserted (such that an SMEM/FMEM read/write/clear

state is enabled), the self-calibration cycle does not begin.

The time required to self-calibrate is dependent on both the

DAC clock frequency and the value of CALCLK. Because self-

calibration requires more time than ordinary operation, the

DAC clock is divided into a slower version and used to step

through the process. Time made available to the self-calibration

algorithm directly impacts its ability to provide accurate results.

A maximum fixed division ratio (4096) corresponds to the

minimum default value of CALCLK (0). The division ratio can

be decreased by increasing the value of CALCLK. Each increase

in the value of CALCLK reduces the DAC clock division factor

(and, therefore, the time made available to self-calibration) by

50%. With CALCLK at its maximum value (7), the divide ratio

declines to its minimum value (32).

With CALCLK at its default value, self-calibration requires

approximately 100 ms at a DAC clock frequency of 100 MHz.

This time can be reduced to under 0.8 ms if CALCLK = 7. Time

scales relative to DAC clock frequency.

Performance Effects of Calibration

Harmonic distortion for low frequency outputs is primarily a

function of DAC linearity. Figure 10 to Figure 12 show the

harmonic distortion performance of the AD9726.

Figure 10 shows a 1 MHz full-scale output tone. The output

drives a unique low-pass and high-pass filter called a diplexer.

This type of filter presents a uniform 50 Ω load to the DAC and

splits the output signal into low and high frequency paths. The

diplexer's low-pass output passes the 1 MHz fundamental but

attenuates higher frequencies, and the diplexer's high-pass out-

put passes higher frequencies and attenuates the 1 MHz funda-

mental. Figure 10 also shows the diplexer's low-pass output.

Here the noise floor is higher than the harmonic distortion

because with a high power input signal, attenuation is required

by the spectrum analyzer.

Figure 11 shows the diplexer's high pass output where the

attenuated input signal can be seen. The spectrum analyzer

attenuation has also been reduced, which lowers the noise

floor. Harmonic products at integer multiples of the funda-

mental are thus revealed. This is the response using the

AD9726 in an uncalibrated state.

Figure 12 shows a response using the AD9726 in a calibrated

state. Harmonic distortion due to the nonlinearities of the

digital-to-analog conversion have been virtually eliminated.

SYNC LOGIC OPERATION AND PROGRAMMING

Recall that a fixed set-up and hold timing relationship between

the data clock input and the data bus must be established and

maintained. Recall also that the data bus and the DAC clock

must be frequency locked. Because of the sync logic, however,

the phase relationship between the data bus and the DAC clock

is internally optimized. Therefore, data arrival propagation

delays and concern about data transitions near the sampling

instant are eliminated.

Synchronization is automatically enabled upon reset. Once data

arrives and synchronization has been achieved, the sync logic

continuously monitors itself so that automatic adjustments are

made if phase drifts occur over time and/or temperature,

automatic adjustments are made.

Note that the sync function and operation of the sync logic

block are transparent, automatic, and ongoing. No programming

is required. For applications where it is useful, however, the

following programmable control is provided.

SYNC Operating States

The sync logic can operate in one of three possible modes. The

default mode is fully automatic.

Fully automatic synchronization is accomplished by demulti-

plexing the incoming data stream into four channels, each

containing every fourth data-word. Data-words are present for

four DAC clock cycles. Data is remultiplexed by sampling each

channel with the optimum DAC clock cycle.

Initial synchronization is first established through a hardware

reset. This also fully enables the synchronization logic to mon-

itor and resynchronize, as necessary. The AD9726 resynchro-

nizes only if conditions change enough to alter the phase

between the data bus and the DAC clock by more than one full

clock cycle. In this event, an internal alarm occurs and is

followed by an automatic update. During resynchronization,

two data-words are typically lost or repeated.

In addition to fully automatic mode, two semi-automatic modes

are available.

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