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AD9726

Rev. A | Page 19 of 24

Linearity CALDACs operate inversely from their input; that is,

as their binary input value increases, the magnitude of their

current contribution seen at the AD9726 output decreases. Gain

CALDACs are an exception to this. Their contribution seen at

the AD9726 output is in direct proportion to their binary input.

Gain CALDACs are also half strength as compared to linearity

CALDACs, but they are intended to be used together as a unit

and thus provide twice the current adjustment range in sum

total.

Calibration Memory

During production testing, the linearity of the AD9726 is

measured and optimized. Values for all CALDACs are perma-

nently stored in nonvolatile factory memory (FMEM). At

reset, all factory memory contents are transferred to static

memory. CALMEM indicates a factory calibrated state

(CALMEM = 10b).

It is also possible at any time to transfer the contents of FMEM

to SMEM by asserting the MEMXFER bit. The XFERSTAT

indicator bit then reports the successful completion of the

transfer cycle, and MEMXFER is cleared.

Note that the MEMXFER bit (and SELFCAL) cannot be

asserted if any other memory access function is currently

enabled (that is, if any Bit [3:0] of Register 0x0F is high).

Attempting to assert MEMXFER (or SELFCAL) in this case

clears any asserted bits in Register 0x0F, but the requested cycle

does not commence.

The factory-to-static memory data transfer cycle requires a

number of DAC clock cycles. The total depends on the value of

CALCLK. This value sets a divider used to create a slow version

of the DAC clock, which is intended to extend the settling time

available to the self-calibration cycle. However, this divided

clock is also used to sequence a memory transfer cycle.

The divider is set to its maximum value with CALCLK at its

default value. A memory transfer cycle requires about 15 ms at a

DAC clock frequency of 100 MHz. This time can be reduced by

50% for every increase in the value of CALCLK.

Accessing Calibration Memory

SMEM or FMEM locations can be read at any time by setting

the SMEMRD or FMEMRD bit in SPI Register 0x0F. Address

and data information can be input and/or output through SPI

SMEM locations can also be written by setting the SMEMWR

bit. Register 0x10 and Register 0x11 are again used for addresses

and data. Any time after the SMEMWR bit has been asserted,

the device reports a user-calibrated state (CALMEM = 11b)

until another action changes the calibration memory status.

To reset static memory at any time, assert the UNCAL bit. All

SMEM locations are then reset to their default values (63).

CALMEM reports an uncalibrated state (CALMEM = 00b).

Note that UNCAL remains asserted (and the contents of SMEM

remains at default values) indefinitely. UNCAL does not clear

itself (like SWRESET) and must be cleared by the user.

Note also that although SPI registers do not depend on the DAC

clock (they use SCLK to sequence the controller state machine),

SMEM and/or FMEM access does require a valid DAC clock.

SMEM/FMEM Read/Write Procedures

Static and factory memory is accessed through the SPI, but it is

not part of the SPI logic. For this reason, memory access requires

a valid DAC clock, while SPI register access does not.

Because the AD9726 SPI is so flexible, allowing single and

multiple byte reads and writes as well as MSB or LSB justified

data, there are perhaps a number of ways in which a user can

access one or more SMEM or FMEM locations.

To avoid potential errors, the following procedures for accessing

static or factory memory should be followed. These procedures

use only single-byte SPI commands to ensure the enabling of

addresses and the sequencing of memory access.

To read from SMEM or FMEM,

Ensure that Bits [3:0] of Register 0x0F are clear.

Begin the sequence by writing the memory address value

to Register 0x10 with a single-byte SPI write command.

Assert the SMEMRD or FMEMRD bit in Register 0x0F

with another single-byte SPI write command.

Import the contents of Register 0x11 using a single-byte

SPI read command.

Clear the SMEMRD or FMEMRD bit with another single-

byte command.

To write to SMEM,

Ensure that Bits [3:0] of Register 0x0F are clear.

Begin the sequence by writing the data value to

Assert the SMEMWR bit using a single-byte SPI write

command.

Place the memory address value in Register 0x10 using a

single-byte SPI write command.

Clear the SMEMWR bit with a fourth single-byte SPI write

command.

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