AD9726

Rev. A | Page 13 of 24

SERIAL PORT INTERFACE

Table 8. SPI Register Map

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00

SDIODIR

DATADIR

SWRESET

SLEEP

PWRDWN

EXTREF

0x02

DATAFMT

DATARATE

INVDCLKI

INVDCLKO

DISDCLKO

SYNCMAN

SYNCUPD

SYNCALRM

0x0E

CALMEM[1]

CALMEM[0]

CALCLK[2]

CALCLK[1]

CALCLK[0]

0x0F

SCALSTAT

SELFCAL

XFERSTAT

MEMXFER

SMEMWR

SMEMRD

FMEMRD

UNCAL

0x10

MEMADR[7]

MEMADR[6]

MEMADR[5]

MEMADR[4]

MEMADR[3]

MEMADR[2]

MEMADR[1]

MEMADR[0]

0x11

MEMDAT[5]

MEMDAT[4]

MEMDAT[3]

MEMDAT[2]

MEMDAT[1]

MEMDAT[0]

0x15

SYNCOUT[1]

SYNCOUT[0]

0x16

SYNCEXT

SYNCIN[1]

SYNCIN[0]

Table 9. SPI Register Bit Default and Descriptions Values

Addr

Name

Bit

I/O

Default

Description

0x00

SDIODIR

7

I

0

0: SDIO is input only (4-wire SPI mode), and SDO is used for output.

1: SDIO is input/output (3-wire SPI mode), and SDO is unused.

DATADIR

6

I

0

0: SPI serial data byte is MSB first format.

1: SPI serial data byte is LSB first format.

SWRESET

5

I

0

1: Software reset: SPI registers (except 0x00) to default values.1

SLEEP

4

I

0

1: Analog outputs temporarily disabled.

PWRDWN

3

I

0

1: Full device power-down; all circuits disabled except SPI.

EXTREF

0

I

0

1: Power-down internal reference: use external reference source.2

0x02

DATAFMT

7

I

0

0: Input data-word is twos complement binary format.

1: Input data-word is unsigned binary format.

DATARATE

6

I

0

0: DDR mode.

1: SDR mode.

INVDCLKI

5

I

0

1: Inverts polarity of data clock input.

INVDCLKO

4

I

0

1: Inverts polarity of data clock output.

DISDCLKO

3

I

0

1: Disables data clock output.

SYNCMAN

2

I

0

1: Enable sync manual mode; disable automatic update.

SYNCUPD

1

I

0

1: Force manual sync update.

SYNCALRM

0

O

0

1: Indicates that sync logic requires update.

0x0E

CALMEM

[5:4]

O

00

2-bit SMEM contents and calibration status indicator.

00: Uncalibrated; SMEM contains default values (63).

01: Self-calibrated; SMEM contains values from self-calibration.

10: Factory-calibrated; SMEM values transferred from FMEM.

11: User-calibrated; SMEM contains user-entered values.

CALCLK

[2:0]

I

000

3-bit self-calibration clock divider ratio. Affects time available for algorithm settling. Each

value increase reduces time by 50%.3

000: Self-calibration clock is DAC clock/4096 (maximum self-calibration settling time for

highest linearity accuracy).

001,010,011: Self-calibration clock is DAC clock/2048,1024,512.

100,101,110: Self-calibration clock is DAC clock/256,128,64.

111: Self-calibration clock is DAC clock/32 (minimum self-calibration settling time for

fastest algorithm completion).

0x0F

SCALSTAT

7

O

0

1: Indicates completion of self-calibration cycle.

SELFCAL

6

I

0

1: Initiates self-calibration cycle.4

XFERSTAT

5

O

0

1: Indicates completion of memory transfer cycle.

MEMXFER

4

I

0

1: Initiates FMEM to SMEM transfer.5

SMEMWR

3

I

0

1: Enable static memory (SMEM) write operation.

SMEMRD

2

I

0

1: Enable static memory (SMEM) read operation.

FMEMRD

1

I

0

1: Enable factory memory (FMEM) read operation.

UNCAL

0

I

0

1: Enable uncalibrated operation; all SMEM to default values.6

0x10

MEMADR

[7:0]

I

00000000

8-bit memory address value for read/write operations.