DSD1791 datasheet(17/56 Pages) TI1

17 / 56 page

DSD1791

SLES072B − MARCH 2003 − REVISED NOVEMBER 2006

www.ti.com

AUDIO DATA INTERFACE

Audio Serial Interface

The audio interface port is a 3-wire serial port. It includes PLRCK (pin 1), PBCK (pin 2), and PDATA (pin 3). PBCK

is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of

the audio interface. Serial data is clocked into the DSD1791 on the rising edge of PBCK. PLRCK is the serial audio

left/right word clock.

The DSD1791 requires the synchronization of PLRCK and the system clock, but does not need a specific phase

relationship between PLRCK and the system clock.

If the relationship between PLRCK and system clock changes more than

±6 PBCK, internal operation is initialized

within 1/fS and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the

system clock is completed.

PCM Audio Data Formats and Timing

The DSD1791 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified.

The data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0], in control

Figure 27 shows a detailed timing diagram for the serial audio interface.

PDATA

t(BCH)

1.4 V

PBCK

PLRCK

t(BCL)

t(LB)

t(BCY)

t(DS)

t(DH)

1.4 V

t(BL)

PARAMETERS

MIN

MAX

UNITS

t(BCY)

PBCK pulse cycle time

t(BCL)

PBCK pulse duration, LOW

t(BCH)

PBCK pulse duration, HIGH

t(BL)

PBCK rising edge to PLRCK edge

t(LB)

PLRCK edge to PBCK rising edge

t(DS)

PDATA setup time

t(DH)

PDATA hold time

—

PLRCK clock data

50%

± 2 bit clocks

Figure 27. Timing of Audio Interface

DSD1791 Datasheet(PDF) 17 Page - Texas Instruments

DSD1791 Datasheet(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL