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DSD1791 Datasheet(PDF) 28 Page - Texas Instruments |
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DSD1791 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 56 page ![]() DSD1791 SLES072B − MARCH 2003 − REVISED NOVEMBER 2006 www.ti.com 28 In DSD mode, these bits select the speed of the bit clock for DSD data coming into the analog FIR filter. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 21 R/W 0 0 1 0 1 0 1 RSV RSV RSV RSV RSV DZ1 DZ0 PCMZ R/W: Read/Write Mode Select When R/W = 0, a write operaton is performed. When R/W = 1, a read operaton is performed. Default value: 0 DZ[1:0]: DSD Zero Output Enable These bits are available for read and write. Default value: 00 DZ[1:0] Zero Output Enable 00 Disabled (default) 01 Even pattern detect 1x 96H pattern detect The DZ bits enable or disable the output zero flags, and select the zero pattern in the DSD mode. PCMZ: PCM Zero Output Enable This bit is available for read and write. Default value: 1 PCMZ = 0 PCM zero output disabled PCMZ = 1 PCM zero output enabled (default) The PCMZ bit enables or disables the output zero flags in the PCM mode and the external DF mode. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 22 R 0 0 1 0 1 1 0 RSV RSV RSV RSV RSV RSV ZFGR ZFGL R: Read Mode Select Value is always 1, specifying the readback mode. ZFGx: Zero-Detection Flag where x = L or R, corresponding to the DAC output channel. These bits are available only for readback. Default value: 00 ZFGx = 0 Not zero ZFGx = 1 Zero detected These bits show zero conditions. Their status is the same as that of the zero flags at ZEROL (pin 23) and ZEROR (pin 22). See Zero Detect in the FUNCTIONAL DESCRIPTIONS section. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 23 R 0 0 1 0 1 1 1 RSV RSV RSV ID4 ID3 ID2 ID1 ID0 R: Read Mode Select Value is always 1, specifying the readback mode. ID[4:0]: Device ID The ID[4:0] bits hold a device ID in the TDMCA mode. |
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