DSD1791 datasheet(15/56 Pages) TI1

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DSD1791

SLES072B − MARCH 2003 − REVISED NOVEMBER 2006

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SYSTEM CLOCK AND RESET FUNCTIONS

System Clock Input

The DSD1791 requires a system clock for operating the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input (pin 5). The DSD1791 has a system clock detection circuit

that automatically senses which frequency the system clock is operating. Table 1 shows examples of system clock

frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as

128 fS, the system clock frequency is required over 256 fS.

Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use

a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators

is an excellent choice for providing the DSD1791 system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY

SYSTEM CLOCK FREQUENCY (fSCK) (MHz)

SAMPLING FREQUENCY

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

32 kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1 kHz

5.6488

8.4672

11.2896

16.9344

22.5792

33.8688

48 kHz

6.144

9.216

12.288

18.432

24.576

36.864

96 kHz

12.288

18.432

24.576

36.864

49.152

73.728

192 kHz

24.576

36.864

49.152

73.728

(1)

(1) This system clock rate is not supported for the given sampling frequency.

t(SCKH)

System Clock (SCK)

t(SCKL)

2 V

0.8 V

t(SCY)

PARAMETERS

MIN

MAX

UNITS

t(SCY)

System clock pulse cycle time

t(SCKH) System clock pulse duration, HIGH

t(SCKL) System clock pulse duration, LOW

Figure 24. System Clock Input Timing

Power-On and External Reset Functions

The DSD1791 includes a power-on reset function. Figure 25 shows the operation of this function. With VDD > 2 V,

the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time

VDD > 2 V. After the initialization period, the DSD1791 is set to its default reset state, as described in the MODE

CONTROL REGISTERS section of this data sheet.

The DSD1791 also includes an external reset capability using the RST input (pin 6). This allows an external controller

or master reset circuit to force the DSD1791 to initialize to its default reset state.

Figure 26 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The

RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock

periods. The external reset is especially useful in applications where there is a delay between the DSD1791 power

up and system clock activation.

DSD1791 Datasheet(PDF) 15 Page - Texas Instruments

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