1k

10k

100k

1M

±200

±160

±120

±80

±40

0

40

80

120

160

200

±40

±30

±20

±10

0

10

20

30

40

50

60

Frequency (Hz)

Mag

Phase

C015

V

I

V

f

f

Phase Margin = 64.7

ƒ

Gain Margin = 17.32 dB

1k

10k

100k

1M

±200

±160

±120

±80

±40

0

40

80

120

160

200

±40

±30

±20

±10

0

10

20

30

40

50

60

Frequency (Hz)

Mag

Phase

C014

V

I

V

f

f

Phase Margin = 63.3

ƒ

Gain Margin = 19.58 dB

(20 mV/div)

(1 A/div)

50

55

60

65

70

75

80

85

90

95

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

C018

Design Example

V

V

f

VREF

COMP

7

8

TPS53317

TPS53317

www.ti.com

SLUSAK4D – JUNE 2011 – REVISED JULY 2015

Typical Applications (continued)

Figure 30. Compensation Network Circuit

8.2.1.2.6

Peripheral Component Selection

As described in Table 1, connect a 0.22-µF capacitor from the VREF pin to GND and connect a 0.1-µF bootstrap

capacitor from the SW pin to the BST pin. Because the PGOOD pin is open drain, connect a pullup resistor

between it and the 5-V rail.

8.2.1.3 Application Curves

Figure 31. Efficiency

Figure 32. Load Transient

Figure 33. Bode Plot, No Load

Figure 34. Bode Plot, Full Load

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