BST

SW

PGND

VOUT

VIN

EN

COMP

VREF

TPS53317

REFIN

V5IN

PGOOD

MODE

GND

PGOOD

VTT

5VIN

UDG-11105

PowerPAD

DDR VDDQ IN

EN

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

TPS53317

SLUSAK4D – JUNE 2011 – REVISED JULY 2015

TPS53317 6-A Output, D-CAP+ Mode, Synchronous Step-Down,

Integrated-FET Converter for DDR Memory Termination

1 Features

3 Description

The

TPS53317

device

is

a

FET-integrated

1

•

TI proprietary Integrated MOSFET and Packaging

synchronous buck regulator designed mainly for DDR

Technology

termination. It can provide a regulated output at ½

•

Supports DDR Memory Termination with up to 6-A

Continuous Output Source or Sink Current

TPS53317

device

employs

D-CAP+™

mode

operation that provides ease of use, low external

•

External Tracking

component count and fast transient response. The

•

Minimum External Components Count

device can also be used for other point-of-load (POL)

•

1-V to 6-V Conversion Voltage

regulation applications requiring up to 6 A. In

•

D-CAP+™ Mode Architecture

addition, the device supports full, 6-A, output sinking

current capability with tight voltage regulation.

•

Supports All MLCC Output Capacitors and

SP/POSCAP

The device features two switching frequency settings

(600 kHz and 1 MHz), integrated droop support,

•

Selectable SKIP Mode or Forced CCM

external tracking capability, pre-bias startup, output

•

Optimized Efficiency at Light and Heavy Loads

soft discharge, integrated bootstrap switch, power

•

Selectable 600-kHz or 1-MHz Switching

good function, V5IN pin UVLO protection, and

Frequency

supports both ceramic and SP/POSCAP capacitors. It

supports input voltages up to 6.0 V, and output

•

Selectable Overcurrent Limit (OCL)

voltages adjustable from 0.6 V to 2.0 V.

•

Overvoltage, Over-Temperature and Hiccup

Undervoltage Protection

The TPS53317 device is available in the 3.5 mm × 4

mm, 20-pin, VQFN package (Green RoHs compliant

•

Adjustable Output Voltage from 0.6 V to 2 V

and Pb free) with TI proprietary Integrated MOSFET

•

3.5 mm × 4 mm, 20-Pin VQFN Package

and packaging technology and is specified from

–40°C to 85°C.

2 Applications

Device Information(1)

•

Memory Termination Regulator for DDR, DDR2,

DDR3, DDR3L, and DDR4

PART NUMBER

PACKAGE

BODY SIZE (NOM)

TPS53317

VQFN (20)

3.50 mm × 4.00 mm

•

VTT Termination

•

Low-Voltage Applications for 1-V to 6-V Input

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Rails

Simplified Application

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.