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TPS53317

www.ti.com

SLUSAK4D – JUNE 2011 – REVISED JULY 2015

Feature Description (continued)

7.3.5 Protection Features

The TPS53317 device offers many features to protect the converter power train as well as the system

electronics.

7.3.5.1 5-V Undervoltage Protection (UVLO)

The TPS53317 device continuously monitors the voltage on the V5IN pin to ensure that the voltage level is high

enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The

converter starts with approximately 4.3 V and has a nominal 440 mV of hysteresis. If the 5-V UVLO limit is

reached, the converter transitions the phase node into an off function, and the converter remains in the off state

until the device is reset by cycling the 5-V supply until the 5-V POR is reached (2.3-V nominal). The power input

does not have a UVLO function.

7.3.5.2 Power Good Signals

The TPS53317 device has one open-drain power good (PGOOD) pin. During startup, there is a 1-ms power

good high propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low or an undervoltage

condition on V5IN or any other fault is detected.

7.3.5.3 Output Overvoltage Protection (OVP)

In addition to the power good function described above, the TPS53317 device has additional OVP and UVP

thresholds and protection circuits.

converter de-asserts the PGOOD signals and performs the overvoltage protection function. During OVP, the low-

side FET is always on before triggering a negative overcurrent. When a negative OC is also tripped, the low-side

FET is no longer continuously on, and pulsed signals are generated to limit the negative inductor current. When

the VOUT pin voltage drops below 400 mV, the low-side FET turns off and the converter latches off. The

converter remains in the off state until the device is reset by cycling the 5-V supply until the 5-V POR is reached

(2.3-V nominal) or when the EN pin is toggled off and on.

7.3.5.4 Output Undervoltage Protection (UVP)

Output undervoltage protection works in conjunction with the current protection described in the Overcurrent

250-µs delay, the device stops switching and enters hiccup mode. After a hiccup waiting time, a restart is

attempted. If the fault condition is not cleared, hiccup mode operation may continue indefinitely.

7.3.5.5 Overcurrent Protection

Both positive and negative overcurrent protection are provided in the TPS53317 device.

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Overcurrent Limit (OCL)

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Negative OCL

7.3.5.5.1

Overcurrent Limit

If the sensed current value is above the OCL setting, the converter delays the next ON pulse until the current

drops below the OCL limit. Current limiting occurs on a pulse-by-pulse basis. The device uses a valley current

limiting scheme where the DC OCL trip point is the OCL limit plus half of the inductor ripple current. The typical

valley OCL threshold is 7.6 A or 5.4 A (depending on mode selection). The average output current limit

calculation is shown in Equation 4.

During the overcurrent protection event, the output voltage droops if the duty cycle cannot satisfy output voltage

requirements and continues to droop until the UVP limit is reached. Then, the converter de-asserts the PGOOD

pin, and then enters hiccup mode after a 250-µs delay. The converter remains in hiccup mode until the fault is

cleared.

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