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WM8993 Datasheet(PDF) 103 Page - Wolfson Microelectronics plc |
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WM8993 Datasheet(HTML) 103 Page - Wolfson Microelectronics plc |
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103 / 229 page  Production Data WM8993 w PD, November 2010, Rev 4.0 103 See “Clocking and Sample Rates” for more details of the System Clock, CLK_SYS. See “GPIO1 Control” for details of GPIO1 output of OPCLK. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R2 (02h) Power Management (2) 11 OPCLK_EN A 0b GPIO Clock Output Enable 0 = disabled 1 = enabled R6 (06h) Clocking 1 12:9 OPCLK_DIV 0000 GPIO Output Clock Divider 0000 = CLK_SYS 0001 = CLK_SYS / 2 0010 = CLK_SYS / 3 0011 = CLK_SYS / 4 0100 = CLK_SYS / 5.5 0101 = CLK_SYS / 6 0110 = CLK_SYS / 8 0111 = CLK_SYS / 12 1000 = CLK_SYS / 16 1001 to 1111 = Reserved Table 67 OPCLK Control |
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