WM8993 datasheet(107/229 Pages) WOLFSON

107 / 229 page

Production Data

WM8993

PD, November 2010, Rev 4.0

107

INTERRUPTS

The interrupt status flag IRQ is asserted when any un-masked interrupt input is asserted. It

represents the OR’d combination of all the un-masked interrupt inputs. If required, this flag may be

inverted using the IRQ_POL register bit. The IRQ flag can be polled at any time, or may be output

directly on the GPIO1 pin.

An interrupt can be generated by any of the following events described earlier:

•

Button detect input (on GPIO1, GPI7 or GPI8)

•

Accessory detection (MICBIAS1 or MICBIAS2 current / short circuit detect)

•

FLL Lock

•

Temperature Sensor

•

Control Write Sequencer

The interrupt events are indicated by the _EINT register fields described earlier. The interrupt event

flags are latched once set; they are reset by writing a logic ‘1’ to the _EINT register bit. Each of these

can be masked as an input to the IRQ function by setting the associated IM_ register field. Note that

the _EINT register fields are always valid, regardless of the setting of the associated IM_ register

fields.

The interrupt behaviour is driven by edge detection (not level detection) of the un-masked inputs.

Therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt

status flag IRQ will not be triggered again. Note that once the IRQ flag is latched then all subsequent

trigger events will be ignored until it has been reset – see Figure 34.

See “GPIO1 Control” for details of outputting IRQ on the GPIO1 pin.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R18 (12h)

GPIO CTRL

IRQ

Interrupt status (IRQ)

Polarity is determined by IRQ_POL

This bit is read only.

R23 (17h)

GPIO_POL

IRQ_POL

Interrupt status (IRQ) polarity

0 = active high

1 = active low

Table 71 Interrupt (IRQ) Control

Figure 34 GPIO Latch

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