MAX783CSLASHD datasheet(18/28 Pages) MAXIM

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Layout and Grounding

Good layout is necessary to achieve the designed out-

put power, high efficiency, and low noise. Good layout

includes use of a ground plane, appropriate compo-

nent placement, and correct routing of traces using

appropriate trace widths. The following points are in

order of importance:

1. A ground plane is essential for optimum performance.

In most applications, the power supply is located on a

multilayer motherboard, and full use of the four or

more copper layers is recommended. Use the top

and bottom layers for interconnections, and the inner

layers for an uninterrupted ground plane.

2. Keep the Kelvin-connected current-sense traces

short, close together, and away from switching

nodes. See Figure 5. Important: Place the current-

sense resistors close to the IC (less than 10mm

away if possible).

3. Place the LX node components N1, N2, D2, and L1

as close together as possible. This reduces resistive

and switching losses and keeps noise due to

ground inductance confined. Do the same with the

other LX node components N3, N4, D5, and L2.

4. The input filter capacitor C1 should be less than

10mm away from N1’s drain. The connecting cop-

per trace carries large currents and must be at least

2mm wide, preferably 5mm.

Similarly, place C2 close to N3’s drain, and connect

them with a wide trace.

5. Keep the gate connections to the MOSFETs short for

low inductance (less than 20mm long and more than

0.5mm wide) to ensure clean switching.

6. To achieve good shielding, it is best to keep all

high-voltage switching signals (MOSFET gate dri-

ves DH3 and DH5, BST3 and BST5, and the two LX

nodes) on one side of the board and all sensitive

nodes (CS3, CS5, FB3, FB5 and REF) on the other

side.

7. Connect the GND and PGND pins directly to the

ground plane, which should ideally be an inner layer

of a multilayer board.

8. Connect the bypass capacitor C7 very close (less

than 10mm) to the VL pin.

9. Minimize the capacitance at the transformer sec-

ondary. Place D3 and C12 very close to each other

and to the secondary, then route the output to the

IC’s VDD pin with a short trace. Bypass with 0.1µF

close to the VDD pin if this trace is longer than

50mm.

The layout for the evaluation board is shown in the

Evaluation Kit section. It provides an effective, low-

noise, high-efficiency example.

Triple-Output Power-Supply Controller

for Notebook Computers

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