GC5016 datasheet(12/88 Pages) TI

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GC5016

SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005

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13.2 Receive Input Formatter (RINF)

The GC5016 has four 16-bit input ports AI[15..0], BI[15..0], CI[15..0], and DI[15..0]. The formatter converts the

representation of real or complex data at the input pins to a complex format output.

13.2.1 Receive Input Data Formats

Five data formats are supported (see Table 1):

D Full Rate, Real Input, one signal per input port

D Double Rate, Real Input, one signal per two input ports (even and odd)

D Half Rate, Complex Input, one signal per input port

D Full Rate, Complex Input, one signal per two input ports (I and Q)

D Double Rate, Complex Input, one signal per four input ports (Ieven, Qeven, Iodd, Qodd)

NOTE:Full Rate means the sample input rate is equal to the GC5016 clock rate.

Each input port has a receive input data formatter. The data formatter accepts 2s complement format data 16 bits

from its input port and outputs a 16-bit I bus and a 16-bit Q bus (the rinf bus). When there is no data to send, the output

bus is held to zero.

For example:

If the input data is real, at full rate, the Q bus is zero.

If the input data is complex, at half rate, every second time sample is zero.

If the input data is complex at full rate, the I data is expected in port A (or C) and A’s Q bus is zero. The imaginary

data is expected in port B (or D) and B’s I bus is zero.

The input format can be specified to the cmd5016 software by setting pseudo-commands rin_rate and rin_cmplx.

NOTE:Pseudo-commands are user specified variables that the software uses to set the hardware register values.

Table 1 shows the modes, the pseudo-commands, and register variables, programmed through the cmd5016

software.

For example, for the mode with four complex inputs, data from source 1 is entered time multiplexed I, followed by

Q onto port AI. Configuration using the software requires that rin_cmplx be set to 1 and rin_rate be set to 0 (half rate).

Alternatively, if the user wishes to program the hardware register fields directly, rinf_sel_A should be set to 3,

mix_rcv_sel to 0 for channel A, and mix_rcv_cmplx to 0 for channel A (etc., for channels B, C, and D).

Table 1. Receive Input Modes and Controls

INPUT PORTS

SOFTWARE

CONTROLS

FIELDS FOR CHANNELS A, B, C, AND D

rinf_sel / mix_rcv_sel / mix_rcv_cmplx

MODE

rin_cmplx / rin_rate

Four real

0/1

4/0/0

4/1/0

4/2/0

4/3/0

Four complex

1I/1Q

2I/2Q

3I/3Q

4I/4Q

1/0

3/0/0

3/1/0

3/2/0

3/3/0

Two complex

1/1

4/0/1

1/x/x

4/2/1

1/x/x

Two double rate

real

1I(2k)

1I(2k+1)

2I(2k)

2I(2k+1)

0/2

4/0/0

4/1/0

4/2/0

4/3/0

One double rate

complex

I(2k)

Q(2k)

I(2k+1)

Q(2k+1)

1/2

4/0/1

1/x/1

4/2/x

1/x/x

13.2.2 Synchronization for IQ Multiplexed Mode

When I and Q are time multiplexed, a synchronization signal is used to determine which sample is I and which is Q.

The input data is delayed by one cycle to form the I stream and is directly output for the Q stream. Thus far the data

stream is (I0,Q0), (Q0, I1), (I1, Q1), — where I0 is the real portion of the sample at time 0. Then every other complex

sample is zeroed using receive interpolation as discussed below, so that the stream is now (I0,Q0), (0,0), (I1,Q1),

(0,0). — The timing for proper receive interpolation sync is shown in the next section.

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