GC5016 datasheet(20/88 Pages) TI

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GC5016

SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005

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D An input swap RAM

D 15 common-programmed FIR filter cells

D A special 16th FIR end cell, and back-end control RAM

D A common control and address generator

D Accumulator logic

D An output gain shift, round, and limit block

Each PFIR can process real or complex data.

Clock

Generator

CICsync

CKmaster

Fck

16x18-Bit

Tap Delay Ram

16x16-Bit

Coef

RAM

PFIR Filter

Cell #1

Accumulator

PFIR Filter

Cell #16

Control

Data

Out

Data In

Control and

Address

Generator

• • •

16x18-Bit

Tap Delay Ram

Figure 10. Programmable Filter Block Diagram

Each FIR cell contains:

D A forward 16x18-bit (16 words with 18-bit width) tap delay RAM

D A backward 16 x 18-bit tap delay RAM (used for symmetric filters)

D A pre-adder with 18-bit output (limits the data to 17-bits when using forward and reverse RAMs with symmetric

filters)

D A 16x16-bit filter coefficient RAM

D A 16-bit x 18-bit (delay and coefficient) multiplier

D A 38-bit sum chain_adder

The output of the sum chain adder in cell # 1 is sent to a 42 bit accumulator. The accumulator output is then shifted

0−7 bits, rounded and limited. The 20-bit accumulator output is sent to the gain section.

The PFIR sections can be programmed independently for each channel.

The filter coefficients can be arranged in banks, allowing the user to change between multiple filter sets rapidly and

synchronously. Two sets of coefficients might be used in an adaptive application. While one set of FIR coefficients

is being used ,the other set is being updated over the control port.

The filter computes 16 taps (32 if symmetric) per clock cycle. The number of clocks available per output sample is

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