GC5016 datasheet(18/88 Pages) TI

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GC5016

SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005

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a) Plot Without Dither or Phase Initialization

b) Plot With Dither and Phase Initialization

−150

−100

−50

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency − fS

NCO OUTPUT POWER

FREQUENCY

−107 dB

−150

−100

−50

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency − fS

NCO OUTPUT POWER

FREQUENCY

−121 dB

Figure 8. NCO Peak Spur Plot

The worst-case NCO spurs at −113 dB to −116 dB, such as the one shown in Figure 7(b), are due to a few frequencies

that are related to the sampling frequency by multiples of fCK/96 and fCK/124. In these cases, the rounding errors

in the sine/cosine lookup table repeat in a regular fashion, thereby concentrating the error power into a single

frequency, rather than spreading it across the spectrum. These worst-case spurs can be eliminated by selecting an

initial phase that minimizes the errors or by changing the tuning frequency by a small amount (50 Hz). Setting the

initial phase register value to 4 for multiples of fCK/96 or fCK/124 (and to 0 for other frequencies) results in spurs below

−115 for all frequencies.

Figure 8 shows the maximum spur levels as the tuning frequency is scanned over a portion of the frequency range

with the peak hold function of the spectrum analyzer turned on. Notice that the peak spur level is −107 dB before

dithering and is −121 dB after dithering has been turned on and the phase initialization described above has been

used.

Double rate processing is done by sending time samples (2k) to mixer A and time samples (2k+1) to mixer B. The

frequency is tuned to freq = (248) x F/fCK, where F is the desired tuning frequency and fCK is the chip’s clock rate as

before. The 16-bit phase offset for mixer A is set to phase = (216) x Ph/2

π, where Ph is the desired phase in radians

ranging between 0 and 2

π. The phase offset for mixer B is set to phase = (216) x Ph/2π + (215) x F/fCK. Note that the

second mixer phase offset is one frequency step at the sample rate of 2 fCK hence 215 rather than 216 scaling. The

configuration software automatically calculates these.

13.6.1 CIC Decimate Filter

The Cascade Integrator Comb (CIC) filter is a 5 stage decimating filter. The CIC filter is set to decimation mode using

the register variable cic_rcv. Each CIC channel contains two CIC filters (one for I and one for Q) allowing input rates

of CK complex samples per second. The CIC filter has several sections: scaling, integration, rate change, comb

filtering, and output scaling. The two CIC filter sections have special logic used in the double rate mode. The double

rate mode is discussed in a later section.

The mixer IQ input is scaled to the 60 bit range using cic_shift. The shifted mixer data is then input to the 5 integrator

M=1 stages. The 5th integrator is decimated in the rate changer, by ncic samples. The cic scaling is based on shifting

the input data to compensate for the 5 integrator stages’ (cic_dec ^ 5) gain.

Ncic = cic_dec − 1

The decimation logic samples the integrator output every cic_dec clocks. The cic_dec value can be set between 1

and 256. The value of cic_dec can actually be programmed up to 4096 but the gain restrictions normally limit the

usable range to 256 (up to 1024 in unusual circumstances).

[1]Hogenhauer, Eugene V., An Economical Class of Digital Filters for Decimation and Interpolation, IEEE transactions on Acoustics, Speech and

Signal Processing, April 1981.

GC5016 Datasheet(PDF) 18 Page - Texas Instruments

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