LAN89218 datasheet(29/148 Pages) MICROCHIP

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DS60001255B-page 29

LAN89218

3.7

Host Bus Operations

3.7.1

32-BIT VS. 16-BIT HOST BUS WIDTH OPERATION

The LAN89218 can be configured to communicate with the host bus via either a 32-bit or a 16-bit bus. The external

strap D32/nD16 (on the EEDIO pin) is used to select between the two modes. 32-bit mode is the native environment

for the LAN89218 Ethernet controller and no special requirements exist for communication in this mode. However,

when this part is used in the 16-bit mode, two writes or reads must be performed back to back to properly

communicate.

The bus width is set by strapping the EEDIO pin; this setting can be read from bit 2 of the HW_CFG—Hardware

Configuration Register.

3.7.2

16-BIT BUS WRITES

The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. This

DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit

write). No ordering requirements exist. The processor can access either the low or high word first, as long as the

next write is performed to the other word. If a write to the same word is performed, the LAN89218 disregards the

transfer.

3.7.3

16-BIT BUS READS

The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. This

DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit

read). No ordering requirements exist. The processor can access either the low or high word first, as long as the

next read is performed from the other word. If a read to the same word is performed, the data read is invalid and

should be re-read. This is not a fatal error. The LAN89218 will reset its read counters and restart a new cycle on the

next read. The Upper 16 data pins (D[31:16]) are not driven by the LAN89218 in 16-bit mode. These pins have

internal pull-downs and the signals are left in a high-impedance state.

3.7.4

MIXED ENDIAN SUPPORT

In order to allow flexibility with a range of designs, the LAN89218 supports dynamic bus endianness selection.

Support for big and little endian host byte ordering is provided based on the END_SEL signal. This signal has the

same timing characteristics as FIFO_SEL and the address line input pins. When END_SEL is low, bus accesses

utilize little endian byte ordering. When END_SEL is high, bus accesses utilize big endian byte ordering. In a typical

application, END_SEL may be connected to a high-order address line, making the endian selection address-based.

This highly flexible interface provides mixed endian access for registers and memory for both PIO and host DMA

access. For example, PIO transfers to/from the host control and status registers can utilize a different byte ordering

than host DMA transactions to/from the receive and transmit data FIFOs.

In addition to mixed endian support, the LAN89218 provides a word swap function, as described in Section 3.7.5.

The word swap function combined with the endianness select bits described above determines how the Data/Status

FIFOs and CSR host access byte ordering is applied. Table 3-9 describes the various operation modes of the

endianness and word swap ordering logic. Figure 3-10 illustrates the FIFO access byte ordering under various

endianness and word swap settings. Refer to Section 3.7.5 for additional details.

3.7.5

WORD SWAP FUNCTION

In addition to mixed endian functionality, the LAN89218 supports a Word Swap Function when its Host Bus Interface

is configured to operate in 16-bit mode. This feature is controlled by the Word Swap register, which is described in

Section 5.3.17. This register affects how words on the data bus are written to or read from the Control and Status

Registers and the Transmit and Receive Data/Status FIFOs.

Logic within LAN89218 reorders bytes based on the host bus width (D32/nD16 strap), the setting of the

WORD_SWAP register (16-bit mode of operation only), the state of the endian select signal (END_SEL), and the

Note:

All internal buses of the LAN89218 are 32-bits wide with little endian byte ordering.

Note:

The Word Swap register only takes effect when the LAN89218 is configured to operate in 16-bit mode. In

32-bit mode, this register is ignored and the upper data bits, D[31:16], are always mapped to the high-order

word, and the lower data bits, D[15:0], are always mapped to the low-order word.

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