LAN89218 datasheet(43/148 Pages) MICROCHIP

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DS60001255B-page 43

LAN89218

3.11

Detailed Reset Description

The LAN89218 has five reset sources:

• Power-On Reset (POR)

• Hardware Reset Input Pin (nRESET)

• Soft Reset (SRST)

• PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)

• PHY Soft Reset via PHY Basic Control Register (PHY REG 0.15)

Table 3-12 shows the effect of the various reset sources on the LAN89218 's circuitry.

Note 1:

After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status Register”

(PHY Reg. 1.2) is set before attempting to transmit or receive data.

Note 2:

After a POR, nRESET or SRST, the LAN89218 will automatically check for the presence of an external

EEPROM. After any of these resets the application must verify that the EPC Busy Bit (E2P_CMD, bit 31) is

cleared before attempting to access the EEPROM, or change the function of the GPO/GPIO signals, or

before modifying the ADDRH or ADDRL registers in the MAC.

Note 3:

HBI - “Host Bus Interface”, NASR - Not affected by software reset.

3.11.1

POWER-ON RESET (POR)

A Power-On reset occurs whenever power is initially applied to the LAN89218, or if power is removed and reapplied

to the LAN89218. A timer within the LAN89218 will assert the internal reset for a maximum of 25 ms after the supply

voltage reaches the minimum operational voltage. The READY bit in the PMT_CTRL register can be read from the

host interface and will read back a ‘0’ until the POR is complete. Upon completion of the POR, the READY bit in

PMT_CTRL is set high, and the LAN89218 can be configured via its control registers. Refer to Section 7.2 for details

on the operational supply voltage range.

TABLE 3-12:

RESET SOURCES AND AFFECTED CIRCUITRY

Reset Source

PLL

HBI

(see Note 3)

NASR

Registers

(see Note 3)

MIL

MAC

PHY

(see Note 1)

EEPROM MAC

ADDR. Reload

(see Note 2)

Config.

Straps

Latched

POR

nRESET

SRST

PHY_RST

PHY REG 0.15

Note:

While the internal power-on reset circuit may assert during brown-out conditions, this is not guaranteed.

For proper operation in applications where brown-outs may occur, use of an external reset circuit is recom-

mended.

Note:

Following deassertion of a power-on reset, the READY bit in PMT_CTRL will be set (high -”1”) within 25

ms. If the software driver polls this bit and it is not set within 100 ms, then an error condition occurred.

Note:

In order for valid device configuration strap inputs to be read at power-on, the configuration strap input volt-

age levels must be stable and ready to be read (latched) within 15 ms (typical) of the deassertion of POR

reset. Device configuration straps are also latched as a result of nRESET assertion. Refer to Section 6.8

and Section 3.11 for additional details.

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