LAN89218 datasheet(92/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 92

 2008-2015 Microchip Technology Inc.

5.3.18

FREE_RUN—FREE-RUN 25MHZ COUNTER

This register reflects the value of the free-running 25 MHz counter.

5.3.19

RX_DROP– RECEIVER DROPPED FRAMES COUNTER

This register indicates the number of receive frames that have been dropped.

Offset:

9Ch

Size:

32 bits

Bits

Description

Type

Default

31:0

Free Running SCLK Counter (FR_CNT):

This field reflects the value of a free-running 32-bit counter. At reset the

counter starts at zero and is incremented for every 25 MHz cycle. When the

maximum count has been reached the counter will rollover. When read in 16-

bit mode the count value is latched on the first read.

Note:

The FREE_RUN counter can take up to 160 ns to clear after a

reset event.

Note:

This counter will run regardless of the power management states

D0, D1 or D2.

Offset:

A0h

Size:

32 bits

Bits

Description

Type

Default

31:0

RX Dropped Frame Counter (RX_DFC). This counter is incremented every

time a receive frame is dropped. RX_DFC is cleared on any read of this regis-

ter.

An interrupt can be issued when this counter passes through its halfway point

(7FFFFFFFh to 80000000h).

00000000h

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