LAN89218 datasheet(10/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 10

 2008-2015 Microchip Technology Inc.

2.1

Pin List

TABLE 2-1:

HOST BUS INTERFACE SIGNALS

Name

Symbol

Buffer Type

# Pins

Description

Host Data High

D[31:16]

I/O8

(PD)

Bi-directional data port.

Note that Pull-downs are disabled in 32-bit mode.

Host Data Low

D[15:0]

I/O8

Bi-directional data port.

Host Address

A[7:1]

7-bit Address Port. Used to select Internal CSR’s and TX

and RX FIFOs.

Read Strobe

nRD

Active low strobe to indicate a read cycle.

Write Strobe

nWR

Active low strobe to indicate a write cycle. This signal,

qualified with nCS, is also used to wakeup the LAN89218

when it is in a reduced power state.

Chip Select

nCS

Active low signal used to qualify read and write opera-

tions. This signal qualified with nWR is also used to

wakeup the LAN89218 when it is in a reduced power

state.

Interrupt

Request

IRQ

O8/OD8

Programmable Interrupt request. Programmable polarity,

source and buffer types.

FIFO Select

FIFO_SEL

When driven high all accesses to the LAN89218 are to

the RX or TX Data FIFOs. In this mode, the A[7:3] upper

address inputs are ignored.

Endianness

Select

END_SEL

(PD)

Endianness Select: When low, all host bus accesses

follow little endian byte ordering. When high, all accesses

follow big endian byte ordering.

This signal is qualified with nCS and nRD for read opera-

tions, and is qualified with nCS and nWR for write opera-

tions. This signal has the same timing characteristics as

the address inputs.

Note:

This signal is pulled low internally and may be

left unconnected or connected to ground for

compatibility with earlier devices.

TABLE 2-2:

LAN INTERFACE SIGNALS

Name

Symbol

Buffer Type

# Pins

Description

TPO+

AIO

Transmit Positive Output (normal)

Receive Positive Input (reversed)

TPO-

AIO

Transmit Negative Output (normal)

Receive Negative Input (reversed)

TPI+

AIO

Receive Positive Input (normal)

Transmit Positive Input (reversed)

TPI-

AIO

Receive Negative Input (normal)

Transmit Negative Output (reversed)

PHY External Bias

Resistor

EXRES1

Must be connected to ground through a 12.4 kΩ

1% resistor.

Note:

The pin names for the twisted pair pins shown above apply to a normal connection. If HP Auto-MDIX is

enabled and a reverse connection is detected, or a reverse connection is manually selected, the input pins

become outputs, and vice-versa, as indicated in the descriptions.

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