LAN89218 datasheet(40/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 40

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3.10

Power Management

The LAN89218 supports power-down modes to allow applications to minimize power consumption. The following

sections describe these modes.

3.10.1

SYSTEM DESCRIPTION

Power is reduced to various modules by disabling the clocks as outlined in Table 3-11. All configuration data is saved

when in either of the two low power states. Register contents are not affected unless specifically indicated in the

3.10.2

FUNCTIONAL DESCRIPTION

There is one normal operating power state, D0 and there are two power saving states: D1, and D2. Upon entry into

either of the two power saving states, only the PMT_CTRL register is accessible for read operations. In either of the

power saving states the READY bit in the PMT_CTRL register will be cleared. Reads of any other addresses are

forbidden until the READY bit is set. All writes, with the exception of the wakeup write to BYTE_TEST, are also

forbidden until the READY bit is set. Only when in the D0 (Normal) state, when the READY bit is set, can the rest

of the device be accessed.

In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the

PMT_CTRL register can be read to determine which LAN89218 device is driving the PME signal.

When the LAN89218 is in a power saving state (D1 or D2), a write cycle to the BYTE_TEST register will return the

LAN89218 to the D0 state. Table 7-3 shows the power consumption values for each power state.

After issuing a write to the BYTE_TEST register to wake the LAN89218 from a power-down state, the READY bit in

PMT_CTRL will assert (set High) within 2 ms.

3.10.2.1

D1 Sleep

Power consumption is reduced in this state by disabling clocks to portions of the internal logic as shown in Table 3-11.

In this mode the clock to the internal PHY and portions of the MAC are still operational. This state is entered when

the host writes a '01' to the PM_MODE bits in the Power Management (PMT_CTRL) register. The READY bit in

PMT_CTRL is cleared when entering the D1 state.

Wake-up frame and Magic Packet detection are automatically enabled in the D1 state. If properly enabled via the

WOL_EN and PME_EN bits, the LAN89218 will assert the PME hardware signal upon the detection of the wake-up

frame or magic packet. The LAN89218 can also assert the host interrupt (IRQ) on detection of a wake-up frame or

magic packet. Upon detection, the WUPS field in PMT_CTRL will be set to a 10b.

Note:

The LAN89218 must always be read at least once after power-up, reset, or upon return from a power-sav-

ing state, otherwise write operations will not function.

Note:

When the LAN89218 is in a power saving state, a write of any data to the BYTE_TEST register will wake-

up the device. DO NOT PERFORM WRITES TO OTHER ADDRRESSES while the READY bit in the

PMT_CTRL register is cleared.

Note:

Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If the software

driver polls this bit and it is not set within 100 ms, then an error condition occurred.

Note:

The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of

PME_EN.

Note:

Wake-up frame and Magic Packet detection is automatically enabled when entering the D1 state. For

wake-up frame detection, the wake-up frame filter must be programmed before entering the D1 state (see

Section 3.5). If used, the host interrupt and PME signal must be enabled prior to entering the D1 state.

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