TUSB422 datasheet(8/71 Pages) TI1

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VDD pin

VCONN pin

Internal

POR

VDD(min)

VDD(max)

VCONN(max)

TINT_N_LOW

INT_N pin

VDD_I2C

VOL(min)

Vinternal

TUSB422

SLLSEW6 – NOVEMBER 2016

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Timing Requirements (continued)

MIN

NOM

MAX

UNIT

tHIGH

High period of SCL

0.26

µs

tSU;STA

Setup time for a repeated start

condition

0.26

µs

tHD;DAT

Data Hold Time

µs

tSU;DAT

Data setup time

µs

tSU;STOP

Setup time for STOP condition

0.26

µs

tBUF

Bus free time between STOP and

START condition

0.5

µs

tVD;DAT

Data valid time

0.45

µs

tVD;ACK

Data valid acknowledge time

0.45

µs

tR_I2C

Rise time of both SDA and SCL

30% to 70%

120

tF_I2C

Fall time of both SDA and SCL

70% to 30%

120

VCONN Fault

tVCONN_FAULT_DLY

Delay from VCONN fault detected to

Vconn fault status flag set

µs

tVCONN_OPEN

Delay from VCONN fault detected to

Vconn switch opened

Power-Up Requirements

tINT_N_LOW

Time from VDD (min) to TUSB422

asserts INT_N low.

Measured from VDD(min) to INT_N pin

at VOL(min).

tVDD_RISE

VDD rise time

Measured from 0 V to VDD(min)

Sampling timings

tCC_SAMPLE_RATE

Delay from VCONN fault detected to

Vconn fault status flag set

CC_SAMPLE_RATE = 2'b01

tVBUSINRATE

The sampling interval of VBUS Voltage CC_SAMPLE_RATE = 2'b01

2.2

Figure 1. Power-Up Timing

TUSB422 Datasheet(PDF) 8 Page - Texas Instruments

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