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LH155BA Datasheet(PDF) 27 Page - Sharp Corporation |
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LH155BA Datasheet(HTML) 27 Page - Sharp Corporation |
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27 / 51 page ![]() LH155BA 27 The LH155BA has a lot of commands, as shown in the list of commands, and each command is explained in detail as follows. Data codes and command codes are defined as follows and the execution of commands must be made in the chip selection state (CSB = "L"). (For example X address) RS * Command Codes * RS = "0" : RAM data access (Refer to Sections 4.2. and 4.3..) RS = "1" : Register access (Refer to Sections 4.4. through 4.17..) The undefined command codes are inhibited. The display RAM data of 8-bit are written in the designated X and Y addresses. 4.2. Data Write to Display RAM The 8-bit contents of display RAM designated in X and Y addresses are read out. Immediately after data are set in X and Y addresses, dummy read is necessary one time. 4.3. Data Read to Display RAM D4 0 D5 0 D6 0 D7 0 AX0 D0 AX1 D1 AX2 D2 AX3 D3 Data Codes D0 CSB D1 D2 D3 D4 D5 D6 D7 Display RAM Write Data D0 D1 D2 D3 D4 D5 D6 D7 Display RAM Read Data RE RDB WRB RS 0010 0 CSB RE RDB WRB RS 0100 0 (At the time of reset : AX3 to AX0 = 0H, read address : 0H) 4.4. X Address Register Set Addresses of display RAM's X direction are set. The values of AX3 to AX0 are usable up to 00H- 0FH, but 10H-FFH are inhibited. When the register setting of SEG output normal/reverse is REF = "0", the data of AX3 to AX0 are addressed to display RAM as they are. When REF = "1", the data of 0FH-(AX3 to AX0)H are addressed to the display RAM. D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 0 AX3 AX2 AX1 AX0 CSB RE RDB WRB RS 1010 0 |
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