AM79C970 datasheet(123/168 Pages) AMD

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AMD

P R E L I M I N A R Y

1-990

Am79C970

If a value other than those listed in the above table is de-

sired, CSR76 and CSR78 can be written after initializa-

tion

complete.

See

the

description

the

appropriate CSRs.

When SSIZE32=1 (BCR20, bit 8), then the software

structures are defined to be 32 bits wide, and the RLEN

and TLEN fields in the initialization block are 4 bits wide,

occupying bits 23–20 (RLEN) and 31–28 (TLEN) and

the value in these fields determines the number of Re-

ceive and Transmit Descriptor Ring Entries (DRE)

which are used in the descriptor rings. Their meaning is

as follows:

R/TLEN

# of DREs

0000

0001

0010

0011

0100

0101

0110

0111

128

1000

256

1001

512

11XX

512

1X1X

512

If a value other than those listed in the above table is de-

sired, CSR76 and CSR78 can be written after initializa-

tion is complete. See the description of the appropriate

CSRs.

RDRA and TDRA

TDRA and RDRA indicate where the transmit and re-

ceive descriptor rings, respectively, begin. When

SSIZE32=1 (BCR20, bit 8), each DRE must be aligned

to a 16-byte boundary (TDRA [3:0]=0, RDRA [3:0]=0).

When SSIZE32=0 (BCR20, bit 8), each DRE must be

aligned to an 8-byte boundary (TDRA [2:0]=0, RDRA

[2:0]=0).

LADRF

The Logical Address Filter (LADRF) is a 64-bit mask that

is used to accept incoming Logical Addresses. If the first

bit in the destination address of the incoming frame (as

received from the wire) is a “1”, the address is deemed

logical. If the first bit is a “0”, it is a physical address and

is compared against the physical address that was

loaded through the initialization block.

A logical address is passed through the CRC generator,

producing a 32-bit result. The high order 6 bits of the

CRC is used to select one of the 64-bit positions in the

Logical Address Filter. If the selected filter bit is set, the

address is accepted and the frame is placed

into memory.

18220C-34

Received Message

Destination Address

CRC

GEN

SEL

MUX

MATCH

MATCH = 1:

Packet Accepted

MATCH = 0:

Packet Accepted

Logical

Address Filter

(LADRF)

32-Bit Resultant CRC

Figure 32. Address Match Logic

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