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AM79C970 Datasheet(PDF) 127 Page - Advanced Micro Devices |
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AM79C970 Datasheet(HTML) 127 Page - Advanced Micro Devices |
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127 / 168 page  AMD P R E L I M I N A R Y 1-994 Am79C970 Transmit Descriptors When SSIZE32=0 (BCR 20, bit 8), then the software structures are defined to be 16 bits wide, and transmit descriptors look like this (CXDA = Current Transmit De- scriptor Address): Table 17. 16-Bit Data Structure Transmit Descriptor Address 15 14 13 12 11 10 9 8 7–0 CXDA+00h TBADR[15:0] CXDA+02h OWN ERR ADD_/ MORE ONE DEF STP ENP TBADR[23:16] NO_ FCS CXDA+04h 1 1 1 1 BCNT CXDA+06h BUFF UFLO EX LCOL LCAR RTRY TDR DEF When SSIZE32=1 (BCR 20, bit 8), then the software structures are defined to be 32 bits wide, and transmit descriptors look like this (CXDA = Current Transmit Descriptor Address): Table 18. 32-Bit Data Structure Transmit Descriptor Address 31 30 29 28 27 26 25 24 23–16 15–4 3–0 CXDA+00h TBADR[31:0] CXDA+04h OWN ERR ADD_/ MORE ONE DEF STP ENP RES 1111 BCNT NO_ FCS CXDA+08h BUFF UFLO EX LCOL LCAR RTRY TDR RES TRC DEF CXDA+0Ch RESERVED TMD0 Bit Name Description 31–0 TBADR Transmit Buffer address. This field contains the address of the transmit buffer that is associated with this descriptor. TMD1 Bit Name Description 31 OWN This bit indicates that the de- scriptor entry is owned by the host (OWN=0) or by the PCnet- PCI controller (OWN=1). The host sets the OWN bit after filling the buffer pointed to by the de- scriptor entry. The PCnet-PCI controller clears the OWN bit af- ter transmitting the contents of the buffer. Both the PCnet-PCI controller and the host must not alter a descriptor entry after it has relinquished ownership. 30 ERR ERR is the OR of UFLO, LCOL, LCAR, or RTRY. ERR is set by the PCnet-PCI controller and cleared by the host. This bit is set in the current descriptor when the error occurs, and therefore may be set in any descriptor of a chained buffer transmission. 29 ADD_FCS_ Bit 29 functions as ADD_FCS NO_FCS when programmed for the default I/O style of PCnet-ISA and when programmed for the I/O style PCnet-PCI controller. Bit 29 functions as NO_FCS when programmed for the I/O style ILACC. ADD_FCS ADD_FCS dynamically controls the generation of FCS on a frame by frame basis. It is valid only if the STP bit is set. When ADD_FCS is set, the state of DXMTFCS is ignored and trans- mitter FCS generation is acti- vated. When ADD_FCS = 0, FCS generation is controlled by DXMTFCS. ADD_FCS is set by the host, and unchanged by the PCnet-PCI controller. This was a reserved bit in the LANCE |
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