AD9144-EBZ datasheet(35/126 Pages) AD

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AD9144

Data Sheet

Rev. A | Page 34 of 125

JESD204B SERIAL DATA INTERFACE

JESD204B OVERVIEW

The AD9144 has eight JESD204B data ports that receive data.

The eight JESD204B ports can be configured as part of a single

JESD204B link or as part of two separate JESD204B links (dual-

link mode) that share a single system reference (SYSREF±) and

device clock (CLK±).

The JESD204B serial interface hardware consists of three layers:

the physical layer, the data link layer, and the transport layer.

These sections of the hardware are described in subsequent

sections, including information for configuring every aspect of

the interface. Figure 35 shows the communication layers

implemented in the AD9144 serial data interface to recover the

clock and deserialize, descramble, and deframe the data before it

is sent to the digital signal processing section of the device.

The physical layer is responsible for establishing a reliable channel

between the transmitter and the receiver, the data link layer is

responsible for unpacking the data into octets and descrambling

the data, and the transport layer receives the descrambled

JESD204B frames and converts them to DAC samples.

There are a number of JESD204B parameters (L, F, K, M, N, NP,

S, HD, and Scrambling) that define how the data is packed and

tell the device how to turn the serial data into samples. These

parameters are defined in detail in the Transport Layer section.

Only certain combinations of parameters are supported. Each

supported combination is called a mode. In total, there are 10

single-link modes supported by the AD9144, as described in

Table 35. In dual-link mode, there are six supported modes, as

described in Table 36. Each of these tables shows the associated

clock rates when the lane rate is 10 Gbps.

For a particular application, the number of converters to use

(M) and the DataRate are known. The LaneRate and number of

lanes (L) can be traded off as follows:

DataRate = (DACRate)/(InterpolationFactor)

LaneRate = (20 × DataRate × M)/L

where LaneRate must be between 1.44 Gbps and 10.64 Gbps.

Achieving and recovering synchronization of the lanes is very

important. To simplify the interface to the transmitter, the

AD9144 designates a master synchronization signal for each

JESD204B link. In single-link mode, SYNCOUT0± is used as the

master signal for all lanes; in dual-link mode, SYNCOUT0± is used

as the master signal for Link 0, and SYNCOUT1± is used as the

master signal for Link 1. If any lane in a link loses synchronization,

a resynchronization request is sent to the transmitter via the

synchronization signal of the link. The transmitter stops sending

data and instead sends synchronization characters to all lanes in

that link until resynchronization is achieved.

DESERIALIZER

DATA LINK

LAYER

TRANSPORT

LAYER

SERDIN0±

SYSREF±

SERDIN7±

DUAL A I DATA[15:0]

DUAL A Q DATA[15:0]

DUAL B Q DATA[15:0]

DUAL B I DATA[15:0]

DAC

SYNCOUT1±

SYNCOUT0±

PHYSICAL

LAYER

DESERIALIZER

FRAME TO

SAMPLES

QBD/

DESCRAMBLER

Figure 35. Functional Block Diagram of Serial Link Receiver

Table 35. Single-Link JESD204B Operating Modes

Mode

Parameter

M (Converter Counts)

L (Lane Counts)

S (Samples per Converter per Frame)

F (Octets per Frame per Lane)

Example Clocks for 10 Gbps Lane Rate

PClock (MHz)

250

Frame Clock (MHz)

1000

500

250

1000

500

250

1000

500

Sample Clock (MHz)

1000

500

250

1000

500

250

1000

500

AD9144-EBZ Datasheet(PDF) 35 Page - Analog Devices

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