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AD9144-EBZ Datasheet(PDF) 95 Page - Analog Devices

Part # AD9144-EBZ
Description  Multiple chip synchronization
PDF  126 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9144-EBZ Datasheet(HTML) 95 Page - Analog Devices

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AD9144
Data Sheet
Rev. A | Page 94 of 125
DEVICE CONFIGURATION REGISTER DESCRIPTIONS
Table 98. Device Configuration Register Descriptions
Address
Name
Bit No.
Bit Name
Settings
Description
Reset
Access
0x000
SPI_INTFCONFA
7
SOFTRESET_M
Soft Reset (Mirror).
0x0
R
6
LSBFIRST_M
LSB First (Mirror).
0x0
R
5
ADDRINC_M
Address Increment (Mirror).
0x0
R
4
SDOACTIVE_M
SDO Active (Mirror).
0x0
R
3
SDOACTIVE
SDO Active.
0x0
R/W
2
ADDRINC
Address Increment. Controls whether
addresses are incremented or decremented
during multibyte data transfers.
0x0
R/W
1
Addresses are incremented during multibyte
data transfers
0
Addresses are decremented during
multibyte data transfers
1
LSBFIRST
LSB First. Controls whether input and output
data are oriented as LSB first or MSB first.
0x0
R/W
1
Shift LSB in first
0
Shift MSB in first
0
SOFTRESET
Soft Reset. Setting this bit initiates a reset.
This bit is autoclearing after the soft reset is
complete.
0x0
R/W
1
Assert soft reset
0x003
CHIPTYPE
[7:0]
CHIPTYPE
The product type is “High Speed DAC”, which
is represented by a code of 0x04.
0x4
R
0x004
PRODIDL
[7:0]
PRODIDL
Product Identification Low.
0x44
R
0x005
PRODIDH
[7:0]
PRODIDH
Product Identification High.
0x91
R
0x006
CHIPGRADE
[7:4]
PROD_GRADE
Product Grade.
0x0
R
[3:0]
DEV_REVISION
Device Revision.
0x6
R
0x008
SPI_PAGEINDX
[7:2]
RESERVED
Reserved.
0x0
R
[1:0]
DUAL_PAGE
Dual Paging. Selects which dual DAC pair is
accessed and written to when changing
digital features, such as digital gain, dc offset,
NCO FTW, and others. This paging affects
Register 0x013 to Register 0x014,
Register 0x034 to Register 0x03d,
Register 0x050 to Register 0x064,
Register 0x110 to Register 0x124, and
Register 0x135 to Register 0x14D.
0x3
R/W
0b01
Read and write Dual A
0b10
Read and write Dual B
0b11
Write both duals; read Dual A
0x00A
SCRATCH_PAD
[7:0]
SCRATCHPAD
This register does not affect any functions in
the device and can be used for testing SPI
communication with the part. Any value
written to this register will be read back to
reflect the change unless a reset or power-
cycle occurs.
0x00
R/W
0x011
PWRCNTRL0
7
PD_BG
Reference Power-Down. Powers down the
band gap reference for the entire chip.
Circuits will not be provided with bias
currents.
0x0
R/W
1
Power down reference
6
PD_DAC_0
Powers Down DAC0. Powers down the I-
channel DAC of Dual A.
0x1
R/W
1
Powers down DAC0
5
PD_DAC_1
Powers Down DAC1. Powers down the Q-
channel DAC of Dual A.
0x1
R/W
1
Powers down DAC 1



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