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AD9144-EBZ Datasheet(PDF) 49 Page - Analog Devices

Part # AD9144-EBZ
Description  Multiple chip synchronization
PDF  126 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9144-EBZ Datasheet(HTML) 49 Page - Analog Devices

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AD9144
Data Sheet
Rev. A | Page 48 of 125
Table 46. Single-Link JESD204B Operating Modes
Mode
Parameter
0
1
2
3
4
5
6
7
9
10
M (Converter Count)
4
4
4
4
2
2
2
2
1
1
L (Lane Count)
8
8
4
2
4
4
2
1
2
1
S (Samples per Converter per Frame)
1
2
1
1
1
2
1
1
1
1
F (Octets per Frame, per Lane)
1
2
2
4
1
2
2
4
1
2
K1 (Frames per Multiframe)
32
16/32
16/32
16/32
32
16/32
16/32
16/32
32
16/32
HD (High Density)
1
0
0
0
1
0
0
0
1
0
N (Converter Resolution)
16
16
16
16
16
16
16
16
16
16
NP (Bits per Sample)
16
16
16
16
16
16
16
16
16
16
Example Clocks for 10 Gbps Lane Rate
PClock Rate (MHz)
250
250
250
250
250
250
250
250
250
250
Frame Clock Rate (MHz)
1000
500
500
250
1000
500
500
250
1000
500
Data Rate (MHz)
1000
1000
500
250
1000
1000
500
250
1000
500
1 K must be 32 in Mode 0, Mode 4, and Mode 9. K can be 16 or 32 in all other modes.
Table 47. Dual-Link JESD204B Operating Modes for Link 0 and Link 1
Mode
Parameter
4
5
6
7
9
10
M (Converter Count)
2
2
2
2
1
1
L (Lane Count)
4
4
2
1
2
1
S (Samples per Converter per Frame)
1
2
1
1
1
1
F (Octets per Frame per Lane)
1
2
2
4
1
2
K1 (Frames per Multiframe)
32
16/32
16/32
16/32
32
16/32
HD (High Density)
1
0
0
0
1
0
N (Converter Resolution)
16
16
16
16
16
16
NP (Bits per Sample)
16
16
16
16
16
16
Example Clocks for 10 Gbps Lane Rate
PClock Rate (MHz)
250
250
250
250
250
250
Frame Clock Rate (MHz)
1000
500
500
250
1000
500
Data Rate (MHz)
1000
1000
500
250
1000
500
1 K must be 32 in Mode 4 and Mode 9. K can be 16 or 32 in all other modes.



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