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LM9627 Datasheet(PDF) 31 Page - National Semiconductor (TI) |
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LM9627 Datasheet(HTML) 31 Page - National Semiconductor (TI) |
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31 / 37 page ![]() Confidential 31 www.national.com Timing Information 1.0 DIGITAL VIDEO PORT MASTER MODE TIMING Figure 49. Row Timing Diagram Figure 50. Frame Timing Figure 51. Frame Delay Timing (With Inter Frame Delay). Note a: See Frame Rate Programming section for more details Note b: See Digital Video Port Registers for more details Label Descriptions Min Typ Max t0 pclk period 74.4ns 83.3ns 1.0 µs t1 hsync low level mode pulse mode (116-HsyncAdjust) *pclk (see note a & b) 16 * pclk t2 hsync high level mode pulse mode (664 -HsyncAdjust) *pclk (see note a & b) 764 * pclk t3 first valid pixel data after hsync active HsyncAdjust * pclk (see note a & b) t5 vsync low level mode pulse mode 116 *pclk (see note a & b) 16 * pclk t6 vsync high level mode pulse mode (FNHclk - 116) * pclk (see note a & b) 16 * pclk hsync t1 t2 P0 P1 t3 d[11:0] pclk Pn pclk vsync t5 t6 R2 R3 hsync t2 t1 Rn vsync t5 t6 t2 t1 hsync Fdelayn-2 Inter Frame Delay Frame (n) pclk Fdelayn-1 Fdelayn R0 R1 R2 Rn |
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