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LM9627 Datasheet(PDF) 32 Page - National Semiconductor (TI) |
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LM9627 Datasheet(HTML) 32 Page - National Semiconductor (TI) |
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32 / 37 page ![]() Confidential 32 www.national.com Timing Information (continued) Figure 52. d[11:0], hsync & vsync to Active High pclk Timing Figure 53. d[11:0], hsync & vsync to Active Low pclk Timing The following specifications apply for all supply pins = +3.3V and CL = 10pF unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25 oC (Note 7) Label Descriptions Min Typ Max t1 Rising pclk to Rising hsync, vsync or d[11:0] 25ns t2 Rising pclk to Falling hsync, vsync or d[11:0] 23ns t3 Falling pclk to rising hsync, vsync or d[11:0] 25ns t4 Falling pclk to falling hsync, vsync or d[11:0] 23ns pclk t1 t2 d[11:0] hsync vsync d[11:0] pclk t3 t4 hsync vsync |
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