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Video Amplifier Specifications

The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = T

AC Electrical Characteristics

Note 1:

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate con-

ditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications

and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions

listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2:

All voltages are measured with respect to VSS = vss_ana = vss_od = vss_dig = 0V, unless otherwise specified.

Note 3:

When the voltage at any pin exceeds the power supplies (VIN < VSS or VIN > VDD), the current at that pin should be lim-

ited to 25mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of 25mA.

Note 4:

is dictated by TJmax, the junction-to-ambient thermal resistance (

ΘJA), and the ambient temperature (T

normal operation will be well under the PDMAX of the package.

Note 5:

Human body model is 100pF capacitor discharged through a 1.5k

Ω resistor. Machine model is 220pF discharged through

ZERO Ohms.

Note 6:

See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount”

found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Note 7:

The analog inputs are protected as shown below. Input voltage magnitude up to 500mV beyond the supply rails will not

damage this device. However, input errors will be generated If the input goes above AV+ and below AGND.

Note 8:

Note 9:

Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Symbol

Parameter

Conditions

Min

note 9

Typical

note 8

Max

note 9

Units

Video Amplifier Nominal Gain

64 linear steps

0-15

dB

Symbol

Parameter

Conditions

Min

note 9

Typical

note 8

Max

note 9

Units

Input Clock Frequency

12

48

MHz

T

ch

Clock High Time

@ CLK

max

10

45

ns

Clock Low Time

10

45

ns

Clock Duty Cycle

45/55

55/45

min/max

T

Clock Input Rise and Fall Time

3

ns

F

hclk

Internal System Clock Fre-

quency

1.0

14.0

MHz

T

reset

Reset pulse width

1.0

µs

Frame Rate

1

30

fps

IOP

Pad

VDD

VSS

Internal Circuits