LM9627 datasheet(35/37 Pages) NSC

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Timing Information (continued)

4.0

SERIAL BUS TIMING

Figure 59. I2C Compatible Serial Bus Timing.

The following specifications apply for all supply pins = +3.3V, C

L = 10pF, and sclk = 400KHz unless otherwise noted. Boldface limits

apply for TA = TMIN to TMAX: all other limits TA = 25

oC (Note 7)

PARAMETER

SYMBOL

MIN

MAX

UNIT

sclk clock frequency

fSCLH

400

KHz

Set-up time (repeated) START condition

SU;STA

0.6

µS

Hold time (repeated) START condition

tHD;STA

0.6

µS

LOW period of the sclk clock

tLOW

1.3

µS

HIGH period of the sclk clock

HIGH

0.6

µS

Data set-up time

tSU;DAT

180

Data hold time

tHD;DAT

0.9

µS

Set-up time for STOP condition

SU;STO

0.6

µS

Capacitive load for sda and sclk lines

400

tfDA

SDA

SCLK

tHD;STA

tHD;DAT

tSU;STA

tSU;DAT

tSU;STO

trCL

rCL

tLOW

tHIGH

trCL1

tHIGH

tLOW

trCL1

(1)

= Rp resistor pull-up

= MCS current source pull-up

(1) Rising edge of the first SCLK pulse after an acknowledge bit.

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