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Functional Description (continued)

13.0 SERIAL BUS

The serial bus interface consists of the sda (serial data), sclk

(serial clock) and sadr (device address select) pins. The

LM9627 can operate only as a slave.

The sclk pin is an input, it only and controls the serial interface,

all other clock functions within LM9627 use the master clock pin,

mclk.

13.1

Start/Stop Conditions

The serial bus will recognize a logic 1 to logic 0 transition on the

sda pin while the sclk pin is at logic 1 as the start condition. A

logic 0 to logic 1 transition on the sda pin while the sclk pin is at

logic 1 is interrupted as the stop condition as shown in Figure

27.

Figure 27. Start/Stop Conditions

13.2

Device Address

The serial bus Device Address of the LM9627 is set to 1010101

when sadr is tied low and 0110011 when sadr is tied high. The

value for sadr is set at power up.

13.3

Acknowledgment

The LM9627 will hold the value of the sda pin to a logic 0 during

the logic 1 state of the Acknowledge clock pulse on sclk as

shown in Figure 28.

Figure 28. Acknowledge

13.4

Data Valid

The master must ensure that data is stable during the logic 1

state of the sclk pin. All transitions on the sda pin can only occur

when the logic level on the sclk pin is “0” as shown in Figure 29.

Figure 29. Data Validity

13.5

Byte Format

Every byte consists of 8 bits. Each byte transferred on the bus

must be followed by an Acknowledge. The most significant bit of

the byte is should always be transmitted first. See Figure 30.

13.6

Write Operation

A write operation is initiated by the master with a Start Condition

followed by the sensor’s Device Address and Write bit. When

the master receives an Acknowledge from the sensor it can

transmit 8 bit internal register address. The sensor will respond

with a second Acknowledge signaling the master to transmit 8

write data bits. A third Acknowledge is issued by the sensor

when the data has been successfully received.

The write operation is completed when the master asserts a

Stop Condition or a second Start Condition. See Figure 31.

13.7

Read Operation

A read operation is initiated by the master with a Start Condition

followed by the sensor’s Device Address and Write bit. When

the master receives an Acknowledge from the sensor it can

transmit the internal Register Address byte. The sensor will

respond with a second Acknowledge. The master must then

issue a new Start Condition followed by the sensor’s Device

Address and read bit. The sensor will respond with an Acknowl-

edged followed by the Read Data byte.

The read operation is completed when the master asserts a Not

Acknowledge followed by Stop Condition or a second Start Con-

dition. See Figure 32.

sda

sclk

start condition

stop condition

sda

from master

sda

from sensor

sclk

MSB

ACK

START

Clock pulse

for ACK

sda

sclk

data line

stable;

data valid

change

of data

allowed

data line

stable;

data valid

Figure 30. Serial Bus Byte Format

Figure 31. Serial Bus Write Operation

Figure 32. Serial Bus Read Operation

sclk

sda

MSB

START

ACK

ack signal

from receiver

byte complete

clock line

held low

ack signal

from receiver

ACK

Address

Data

Device

Address

Byte

bold sensor action

Device

Data

Device

Byte

Address

bold sensor action

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