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LM9627 Datasheet(PDF) 24 Page - National Semiconductor (TI) |
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LM9627 Datasheet(HTML) 24 Page - National Semiconductor (TI) |
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24 / 37 page  Confidential 24 www.national.com MEMORY MAP ADDR Register Reset Value Description 00h Reserved for future use. 01h REV 02h Revision Register 02h MCFG0 00h Main Configuration Register 0 03h MCFG1 00h Main Configuration Register 1 04h PCR 00h Power Control Register. 05h VCLKGEN 04h Video Clock Generator 06h VMODE0 00h Video Mode 0 Register 07h VMODE1 00h Video Mode 1 Register 08h VMODE2 00h Video Mode 2 Register 09h SNAPMODE0 00h Snapshot Mode 0 Register 0Ah SNAPMODE1 00h Snapshot Mode 1 Register 0Bh SROWS 00h Scan Window Row Start Register 0Ch SROWE FBh Scan Window Row End Register 0Dh Reserved for future use. 0Eh DROWS 00h Display Window Row Start Register 0Fh DROWE FBh Display Window Row End Register 10h DCOLS 00h Display Window Column Start Register 11h DCOLE A5h Display Window Column End Register 12h DWLSB 32h Display Window LSB Register. 13h ITIMEH 00h Integration Time High Register 14h ITIMEL 00h Integration Time Low Register 15h RDELAYH 00h Row Delay High Register 16h RDELAYL 00h Row Delay Low Register 17h FDELAYH 00h Frame Delay High Register 18h FDELAYL 00h Frame Delay Low Register 19h VGAIN 00h Video Gain Register 1Fh OCR1 00h Offset Compensation Register 1 22h OCR1 00h Offset Compensation Register 1 25h OCR2 00h Offset Compensation Register 2 26h BLCOEFF 00h Black Level Compensation Coefficient Register 27h BPTH0H 00h Bad pixel Threshold 0 High Register 28h BPTH0L 00h Bad pixel Threshold 0 Low Register 29h BPTH1H 00h Bad pixel Threshold 1 High Register 2Ah BPTH1L 00h Bad pixel Threshold 1 Low Register |
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