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ADuC831

WDCON

Watchdog Timer Control Register

SFR Address

C0H

Power-On Default Value

10H

Bit Addressable

Yes

Table XV. WDCON SFR Bit Designations

Bit

Name

Description

PRE3

Watchdog Timer Prescale Bits.

PRE2

The Watchdog timeout period is given by the equation: tWD = (2

PRE

9/f

R/C OSC))

PRE1

≤ PRE ≤ 7; f

R/C OSC = 32 kHz

10% at 25ºC)

PRE0

PRE3 PRE2 PRE1

PRE0 Timeout Period (ms) Action

000

15.6

Reset or Interrupt

000

31.2

Reset or Interrupt

001

62.5

Reset or Interrupt

001

125

Reset or Interrupt

010

250

Reset or Interrupt

010

500

Reset or Interrupt

011

1000

Reset or Interrupt

011

2000

Reset or Interrupt

100

0.0

Immediate Reset

PRE3–0 > 1000

Reserved

WDIR

Watchdog Interrupt Response Enable Bit.

If this bit is set by the user, the watchdog will generate an interrupt response instead of a

system reset when the watchdog timeout period has expired. This interrupt is not disabled by

the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not

being used to monitor the system, it can alternatively be used as a timer. The prescaler is used

to set the timeout period in which an interrupt will be generated.

WDS

Watchdog Status Bit.

Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.

Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.

WDE

Watchdog Enable Bit.

Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user

within the watch dog timeout period, the watchdog will generate a reset or interrupt, depending

on WDIR. Cleared under the following conditions, user writes “0,” Watchdog Reset (WDIR = “0”);

Hardware Reset; PSM Interrupt.

WDWR

Watchdog Write Enable Bit.

To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit

must be set and the very next instruction must be a write instruction to the WDCON SFR.

For example:

CLR

;disable interrupts while writing

;to WDT

SETB WDWR

;allow write to WDCON

MOV

WDCON, #72H ;enable WDT for 2.0s timeout

SETB EA

;enable interrupts again (if rqd)

WATCHDOG TIMER

The purpose of the watchdog timer is to generate a device

reset or interrupt within a reasonable amount of time if the

ADuC831 enters an erroneous state, possibly due to a program-

ming error or electrical noise. The watchdog function can be

disabled by clearing the WDE (Watchdog Enable) bit in the

Watchdog Control (WDCON) SFR. When enabled, the watch-

dog circuit will generate a system reset or interrupt (WDS) if

the user program fails to set the watchdog (WDE) bit within a

predetermined amount of time (see PRE3–0 bits in WDCON).

The watchdog timer itself is a 16-bit counter that is clocked at

32 kHz by the internal R/C oscillator. The watchdog time out

interval can be adjusted via the PRE3–0 bits in WDCON. Full

control and status of the watchdog timer function can be con-

trolled via the watchdog timer control SFR (WDCON). The

WDCON SFR can only be written by user software if the

double write sequence described in WDWR below is initiated

on every write access to the WDCON SFR.

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