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ADUC831BCP Datasheet(PDF) 69 Page - Analog Devices |
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ADUC831BCP Datasheet(HTML) 69 Page - Analog Devices |
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69 / 76 page ![]() REV. 0 ADuC831 –69– 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE tWLWH WR Pulsewidth 400 6tCK – 100 ns 72 tAVLL Address Valid after ALE Low 43 tCK –40 ns 72 tLLAX Address Hold after ALE Low 48 tCK –35 ns 72 tLLWL ALE Low to RD or WR Low 200 300 3tCK –50 3tCK +50 ns 72 tAVWL Address Valid to RD or WR Low 203 4tCK – 130 ns 72 tQVWX Data Valid to WR Transition 33 tCK –50 ns 72 tQVWH Data Setup before WR 433 7tCK – 150 ns 72 tWHQX Data and Address Hold after WR 33 tCK –50 ns 72 tWHLH RD or WR High to ALE High 43 123 tCK –40 6tCK – 100 ns 72 t LLAX DATA MCLK ALE (O) PSEN (O) PORT 2 (O) t LLWL t AVWL t AVLL t QVWX t WHQX t WHLH A0–A7 A16–A23 A8–A15 t WLWH t QVWH WR (O) Figure 72. External Data Memory Write Cycle |
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