ADUC831BCP datasheet(34/76 Pages) AD

34 / 76 page

REV. 0

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ADuC831

SOURCE/SINK CURRENT – mA

DAC LOADED WITH 0000H

DAC LOADED WITH 0FFFH

Figure 24. Source and Sink Current Capability with

VREF = VDD = 3 V

To reduce the effects of the saturation of the output amplifier at

values close to ground and to give reduced offset and gain errors,

the internal buffer can be bypassed. This is done by setting the

DBUF bit in the CFG831 register. This allows a full rail-to-rail

output from the DAC which should then be buffered externally

using a dual supply op-amp in order to get a rail-to-rail output.

This external buffer should be located as near as physically

possible to the DAC output pin on the PCB. Note the unbuffed

mode only works in the 0 to VREF range.

To drive significant loads with the DAC outputs, external buff-

ering may be required (even with the internal buffer enabled),

as illustrated in Figure 25. A list of recommended op-amps is in

Table VI.

ADuC831

DAC0

DAC1

Figure 25. Buffering the DAC Outputs

The DAC output buffer also features a high-impedance disable

function. In the chip’s default power-on state, both DACs are

disabled, and their outputs are in a high-impedance state (or

“three-state”) where they remain inactive until enabled in software.

This means that if a zero output is desired during power-up or

power-down transient conditions, then a pull-down resistor must

be added to each DAC output. Assuming this resistor is in place,

the DAC outputs will remain at ground potential whenever the

DAC is disabled.

ADUC831BCP Datasheet(PDF) 34 Page - Analog Devices