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NSC800N Datasheet(PDF) 29 Page - National Semiconductor (TI) |
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NSC800N Datasheet(HTML) 29 Page - National Semiconductor (TI) |
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29 / 76 page  121 Instruction Set Index (Continued) Alphabetical Assembly Operation Page Mnemonic DI Disable interrupts 54 DJNZd Decrement B and jump relative B i 056 EI Enable interrupts 54 EX (SP)ss Exchange the location (SP) with register ss 50 EX AFA’F’ Exchange the contents of AF and A’F’ 49 EX DEHL Exchange the contents of DE and HL 49 EXX Exchange the contents of BC DE and HL with the contents 50 of B’C D’E’ and H’L’ respectively HALT Halt (wait for interrupt or reset) 54 IM 0 Set interrupt mode 0 54 IM 1 Set interrupt mode 1 55 IM 2 Set interrupt mode 2 55 IN A(n) Load Accumulator with input from device (n) 52 IN r(C) Load register r with input from device (C) 52 INC m1 Increment data in memory location m1 42 INC r Increment register r 37 INC rr Increment contents of register pair rr 43 IND Load location (HL) with input from port (C) decrement HL and B 52 INDR Load location (HL) with input from port (C) decrement HL and B repeat until B e 054 INI Load location (HL) with input from port (C) increment HL decrement B 52 INIR Load location (HL) with input from port (C) increment HL decrement B 53 repeat until B e 0 JP ccnn Jump to location nn if condition cc is true 55 JP nn Unconditional jump to location nn 55 JP (ss) Unconditional jump to location (ss) 55 JR d Unconditional jump relative to PC a d55 JR kkd Jump relative to PC a d if kk true 55 LD AI Load Accumulator with register I contents 32 LD Am2 Load Accumulator from location m2 33 LD AR Load Accumulator with register R contents 32 LD IA Load register I with Accumulator contents 32 LD m1 n Load memory with immediate data n 33 LD m1 r Load memory from register r 32 LD m2 A Load memory from Accumulator 33 LD (nn)rr Load memory location nn with register pair rr 34 LD rm1 Load register r from memory 33 LD rn Load register with immediate data n 32 LD RA Load register R from Accumulator 32 LD rd rs Load destination register rd from source register rs 32 LD rr(nn) Load register pair rr from memory location nn 35 LD rrnn Load register pair rr with immediate data nn 34 LD SPss Load SP from register pair ss 34 LDD Load location (DE) with location (HL) decrement DE HL and BC 50 LDDR Load location (DE) with location (HL) decrement DE HL and BC repeat until BC e 051 LDI Load location (DE) with location (HL) increment DE and HL decrement BC 50 LDIR Load location (DE) with location (HL) increment DE and HL decrement BC 51 repeat until BC e 0 NEG Negate Accumulator (2’s complement) 38 NOP No operation 54 29 |
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