NSC800N datasheet(11/76 Pages) NSC

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80 Functional Description (Continued)

81 REGISTER ARRAY

The NSC800 register array is divided into two parts the

dedicated registers and the working registers as shown in

Figure 2

Main Reg Set

Alternate Reg Set

Accumulator Flags Accumulator Flags

Working

Registers

Interrupt

Memory

Vector I

Refresh R

Index Register IX

Dedicated

Index Register IY

Registers

Stack Pointer SP

Program Counter PC

–

FIGURE 2 NSC800 Register Array

82 DEDICATED REGISTERS

There are 6 dedicated registers in the NSC800 two 8-bit

and four 16-bit registers (see

Figure 3 )

Although their contents are under program control the pro-

gram has no control over their operational functions unlike

the CPU working registers The function of each dedicated

CPU Dedicated Registers

Program Counter PC

(16)

Stack Pointer SP

(16)

Index Register IX

(16)

Index Register IY

(16)

Interrupt Vector Register I

(8)

Memory Refresh Register R

(8)

FIGURE 3 Dedicated Registers

821 Program Counter (PC)

The program counter contains the 16-bit address of the cur-

rent instruction being fetched from memory The PC incre-

ments after its contents have been transferred to the ad-

dress lines When a program jump occurs the PC receives

the new address which overrides the incrementer

There are many conditional and unconditional jumps calls

and return instructions in the NSC800’s instruction reper-

toire that allow easy manipulation of this register in control-

ling the program execution (ie JP NZ nn JR Zd2 CALL

NC nn)

822 Stack Pointer (SP)

The 16-bit stack pointer contains the address of the current

top of stack that is located in external system RAM The

stack is organized in a last-in first-out (LIFO) structure The

pointer decrements before data is pushed onto the stack

and increments after data is popped from the stack

Various operations store or retrieve data on the stack This

along with the usage of subroutine calls and interrupts al-

lows simple implementation of subroutine and interrupt

nesting as well as alleviating many problems of data manip-

ulation

823 Index Register (IX and IY)

The NSC800 contains two index registers to hold indepen-

dent 16-bit base addresses used in the indexed addressing

mode In this mode an index register either IX or IY con-

tains a base address of an area in memory making it a point-

er for data tables

In all instructions employing indexed modes of operation

another byte acts as a signed two’s complement displace-

ment This addressing mode enables easy data table ma-

nipulations

824 Interrupt Register (I)

When the NSC800 provides a Mode 2 response to INTR

the action taken is an indirect call to the memory location

containing the service routine address The pointer to the

address of the service routine is formed by two bytes the

high-byte is from the I Register and the low-byte is from the

interrupting peripheral The peripheral always provides an

even address for the lower byte (LSBe0) When the proc-

essor receives the lower byte from the peripheral it concate-

nates it in the following manner

I Register

External byte

8 bits

The LSB of the external byte must be zero

FIGURE 4a Interrupt Register

The even memory location contains the low-order byte the

next consecutive location contains the high-order byte of

the pointer to the beginning address of the interrupt service

routine

825 Refresh Register (R)

For systems that use dynamic memories rather than static

RAM’s the NSC800 provides an integral 8-bit memory re-

fresh counter The contents of the register are incremented

after each opcode fetch and are sent out on the lower por-

tion of the address bus along with a refresh control signal

This provides a totally transparent refresh cycle and does

not slow down CPU operation

The program can read and write to the R register although

this is usually done only for test purposes

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