NSC800N datasheet(37/76 Pages) NSC

37 / 76 page

126 8-Bit Arithmetic (Continued)

76543210

10100

Timing

M cycles1

T states4

Addressing Mode

SourceRegister

DestinationImplied

Logically OR the contents of the r register and the Accumu-

lator

w A

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Reset

76543210

10110

Timing

M cycles1

T states4

Addressing Mode

SourceRegister

DestinationImplied

XOR

Logically exclusively OR the contents of the r register with

the Accumulator

w A Z r

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Reset

76543210

10101

Timing

M cycles1

T states4

Addressing Mode

SourceRegister

DestinationImplied

INC

Increment register r

w r a 1

S Set if result is negative

Z Set if result is zero

H Set if carry from bit 3

PV Set only if r was X’7F before

operation

N Reset

C NA

76543210

100

Timing

M cycles1

T states4

Addressing Mode

SourceRegister

DestinationRegister

Compare the contents of register r with the Accumulator

and set the flags accordingly

A b r

S Set if result is negative

Z Set if result is zero

H Set if borrow from bit 4

PV Set if result exceeds 8-bit 2’s

complement range

N Set

C Set according to borrow

76543210

10111

Timing

M cycles1

T states4

Addressing Mode

SourceRegister

DestinationImplied

DEC

Decrement the contents of register r

w r b 1

S Set if result is negative

Z Set if result is zero

H Set according to a borrow from

bit 4

PV Set only if r was X’80 prior to

operation

N Set

C NA

76543210

101

Timing

M cycles1

T states4

Addressing Mode

SourceRegister

DestinationRegister

CPL

Complement the Accumulator (1’s complement)

w A

S NA

Z NA

H Set

PV NA

N Set

C NA

NSC800N Datasheet(PDF) 37 Page - National Semiconductor (TI)

NSC800N Datasheet(HTML) 37 Page - National Semiconductor (TI)

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