NSC800N datasheet(32/76 Pages) NSC

32 / 76 page

124 8-Bit Loads

rd rs

Load register rd with rs

w rs

No flags affected

543

Timing

M cycles

T states

Addressing Mode

A I

Load Accumulator with the contents of the I register

w I

S Set if negative result

Z Set if zero result

H Reset

PV Set according to IFF2 (zero if

interrupt occurs during opera-

tion)

N Reset

C Not affected

76543210

11101101

01010111

Timing

M cycles

T states

9 (4 5)

Addressing Mode

I A

Load Interrupt vector register (I) with the contents of A

w A

No flags affected

76543210

11101101

01000111

Timing

M cycles

T states

9 (4 5)

Addressing Mode

A R

Load Accumulator with contents of R register

w R

S Set if negative result

Z Set if zero result

H Reset

PV Set according to IFF2 (zero if

interrupt occurs during opera-

tion)

N Reset

C Not affected

76543210

11101101

01011111

Timing

M cycles

T states

9 (4 5)

Addressing Mode

R A

Load Refresh register (R) with contents of the Accumulator

w A

No flags affected

76543210

11101101

01001111

Timing

M cycles

T states

9 (4 5)

Addressing Mode

r n

Load register r with immediate data n

w n

No flags affected

76543210

110

Timing

M cycles

T states

7 (4 3)

Addressing Mode

Source

Immediate

Destination

m1 r

Load memory from reigster r

w r

No flags affected

76543210

01110

LD (HL) r

Timing

M cycles

T states

7 (43)

Addressing Mode

Source

Destination

43210

LD (IXad) r(for NXe0)

11NX 11101

LD (IYad) r(for NXe1)

111

Timing

M cycles

T states

19 (4 4 3 5 3)

Addressing Mode

Source

Destination

Indexed

NSC800N Datasheet(PDF) 32 Page - National Semiconductor (TI)

NSC800N Datasheet(HTML) 32 Page - National Semiconductor (TI)

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