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NSC800N Datasheet(PDF) 38 Page - National Semiconductor (TI) |
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NSC800N Datasheet(HTML) 38 Page - National Semiconductor (TI) |
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38 / 76 page  126 8-Bit Arithmetic (Continued) 76543210 00101111 Timing M cycles1 T states4 Addressing Mode Implied NEG Negate the Accumulator (2’s complement) A w 0 b A S Set if result is negative Z Set if result is zero H Set according to borrow from bit 4 PV Set only if Accumulator was X’80 prior to operation N Set C Set only if Accumulator was not X’00 prior to operation 76543210 11101101 01000100 Timing M cycles2 T states8 (4 4) Addressing Mode Implied CCF Complement the carry flag CY w CY S NA Z NA H Previous carry PV NA N Reset C Complement of previous carry 76543210 00111111 Timing M cycles1 T states4 Addressing Mode Implied SCF Set the carry flag CY w 1 S NA Z NA H Reset PV NA N Reset C Set 76543210 00110111 Timing M cycles1 T states4 Addressing Mode Implied DAA Adjust the Accumulator for BCD addition and subtraction operations To be executed after BCD data has been oper- ated upon the standard binary ADD ADC INC SUB SBC DEC or NEG instructions (see ‘‘Register Addressing Arith- metic’’ table) S Set according to bit 7 of result Z Set if result is zero H Set according to instructions PV Set according to parity of result N NA C Set according to instructions 76543210 00100111 Timing M cycles1 T states4 Addressing Mode Implied IMMEDIATELY ADDRESSED ARITHMETIC ADD A n Add the immediate data n to the Accumulator A w A a n S Set if result is negative Z Set if result is zero H Set if carry from bit 3 PV Set if result exceeds 8-bit 2’s complement range N Reset C Set if carry from bit 7 76543210 11000110 n Timing M cycles2 T states7 (4 3) Addressing Mode SourceImmediate DestinationImplied ADC A n Add with carry the immediate data n and the Accumulator A w A a n a CY S Set if result is negative Z Set if result is zero H Set if carry from bit 3 PV Set if result exceeds 8-bit 2’s complement range N Reset C Set according to carry from bit 7 38 |
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