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Video Processor Module (Continued)

Offset 10h-13h

Video Upscale Register (R/W)

Reset Value: 00000000h

Provides horizontal and vertical upscale factors of the window.

31:30

Reserved.

29:16

VID_Y_SCL (Video Y Scale Factor). Represents the vertical upscale factor of the video window according to the following

formula:

VID_Y_SCL = 8192 * (Ys - 1) / (Yd - 1)

where:

Ys = Video source vertical size in pixels

Yd = Video destination vertical size in pixels

Note:

Upscale factor must be used. Yd is equal or bigger than Ys. If no scaling is intended, set to 2000h. The actual

scale factor used is VID_Y_SCL/8192, but the formula above fits a given source number of lines into a destination

window size.

Note:

When progressive mixing/blending is programmed (F4BAR0+Memory Offset 4Ch[9] = 0) and the video data is

interlaced, this register should be programmed to 1000h to double the vertical lines,

15:14

Reserved.

13:0

VID_X_SCL (Video X Scale Factor). Represents horizontal upscale factor of the video window according to the following

formula:

VID_X_SCL = 8192 * (Xs - 1) / (Xd - 1)

where:

Xs = Video source horizontal size in pixels

Xd = Video destination vertical size in pixels

Note:

Upscale factor must be used. Xd is equal or bigger than Xs. If no scaling is intended, set to 2000h. The actual

scale factor used is VID_X_SCL/8192, but the formula above fits a given source number of pixels into a destination

window size.

Offset 14h-17h

Video Color Key Register (R/W)

Reset Value: 00000000h

Provides the video color key. The color key can be used to allow irregular shaped overlays of graphics onto video, or video onto graph-

ics, within a scaled video window.

31:24

Reserved.

23:0

VID_CLR_KEY (Video Color Key). The video color key is a 24-bit RGB or YUV value.

•

If the COLOR_CHROMA_SEL bit (F4BAR0+Memory Offset 04h[20]) = 0:

— The video pixel is selected within the target window if the corresponding graphics pixel matches the color key. The

color key in an RGB value.

•

If the COLOR_CHROMA_SEL bit (F4BAR0+Memory Offset 04h[20]) = 1:

— The video pixel is selected within the target window only if it (the video pixel) does not match the color key. The color

key is usually an RGB value. However, if both the CSC_for VIDEO and GV_SEL bits (F4BAR0+Memory Offset 4Ch

bits 10 and 13, respectively) are programmed to 0, the color key is a YUV value (i.e., video is not converted to RGB).

The graphics or video data being compared can be masked prior to the compare via the Video Color Mask register

(described in F4BAR0+Memory Offset 18h).

Offset 18h-1Bh

Video Color Mask Register (R/W)

Reset Value: 00000000h

Provides the video color mask. This value is used to mask bits of the graphics or video stream being compared to the video color key

(described in F4BAR0+Memory Offset 14h). It can be used to allow a range of values to serve as the color key.

31:24

Reserved.

23:0

VID_CLR_MASK (Video Color Mask). This mask is a 24-bit value. Zeros in the mask cause the corresponding bits in the

graphics or video stream to be ignored.

Offset 1Ch-1Fh

Palette (Gamma Correction RAM) Address Register (R/W)

Reset Value: xxxxxxxxh

31:8

Reserved.

7:0

PAL_ADDR (Palette Address). Specifies the address to be used for the next access to the Palette Data register

(F4BAR0+Memory Offset 20h[31:8]). Each access to the data register automatically increments the Palette Address regis-

ter. If non-sequential access is made to the palette, the address register must be loaded between each non-sequential data

block.

Table 6-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)

Bit

Description

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